gem5/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
Gabe Black c240d4af84 The alpha twolf regression was really for tru64, not linux.
--HG--
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini => tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out => tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr
rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini => tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out => tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
extra : convert_revision : 55f9327662e0902925ca14b3260a86f7d211d445
2007-03-11 18:44:36 -04:00

90 lines
1.4 KiB
INI

[root]
type=Root
children=system
checkpoint=
clock=1000000000000
max_tick=0
output_file=cout
progress_interval=0
[serialize]
count=10
cycle=0
dir=cpt.%012d
period=0
[stats]
descriptions=true
dump_cycle=0
dump_period=0
dump_reset=false
ignore_events=
mysql_db=
mysql_host=
mysql_password=
mysql_user=
project_name=test
simulation_name=test
simulation_sample=0
text_compat=true
text_file=m5stats.txt
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=workload
clock=1
cpu_id=0
defer_registration=false
function_trace=false
function_trace_start=0
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
phase=0
progress_interval=0
simulate_stalls=false
system=system
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic
egid=100
env=
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
output=cout
pid=100
ppid=99
system=system
uid=100
[system.membus]
type=Bus
bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
zero=false
port=system.membus.port[0]