878 lines
98 KiB
Text
878 lines
98 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 175308 # Simulator instruction rate (inst/s)
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host_mem_usage 291488 # Number of bytes of host memory used
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host_seconds 302.62 # Real time elapsed on the host
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host_tick_rate 6165281708 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 53051410 # Number of instructions simulated
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sim_seconds 1.865725 # Number of seconds simulated
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sim_ticks 1865725201500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 6623532 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 12798498 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 40602 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 812765 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 11935951 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 14337786 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1014820 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 8457292 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 1010049 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 89220035 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.630402 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.393670 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 65107302 72.97% 72.97% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 10633646 11.92% 84.89% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 6059339 6.79% 91.68% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 2842196 3.19% 94.87% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 2097639 2.35% 97.22% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 698987 0.78% 98.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 396440 0.44% 98.45% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 374437 0.42% 98.87% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 1010049 1.13% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 89220035 # Number of insts commited each cycle
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system.cpu.commit.COM:count 56244494 # Number of instructions committed
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system.cpu.commit.COM:loads 9107208 # Number of loads committed
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system.cpu.commit.COM:membars 227971 # Number of memory barriers committed
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system.cpu.commit.COM:refs 15496285 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 771538 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 56244494 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 667580 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 8696245 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 53051410 # Number of Instructions Simulated
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system.cpu.committedInsts_total 53051410 # Number of Instructions Simulated
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system.cpu.cpi 2.356931 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 2.356931 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses::0 215724 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 215724 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14717.635433 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.423892 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_hits::0 193462 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 193462 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 327644000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103197 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses::0 22262 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 22262 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 4800 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207438500 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080946 # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_misses 17462 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.ReadReq_accesses::0 9298342 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 9298342 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::0 22727.861188 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.930840 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu.dcache.ReadReq_hits::0 7723201 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 7723201 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 35799586000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate::0 0.169400 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::0 1575141 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 1575141 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 491284 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 24690187500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116565 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1083857 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 906002000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses::0 219691 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 219691 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14000 # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency
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system.cpu.dcache.StoreCondReq_hits::0 219688 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 219688 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_miss_latency 42000 # number of StoreCondReq miss cycles
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system.cpu.dcache.StoreCondReq_miss_rate::0 0.000014 # miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_misses::0 3 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_mshr_miss_latency 33000 # number of StoreCondReq MSHR miss cycles
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000014 # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_misses 3 # number of StoreCondReq MSHR misses
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system.cpu.dcache.WriteReq_accesses::0 6154235 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6154235 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency::0 29744.201377 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28089.748800 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_hits::0 4298938 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 4298938 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 55184327582 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate::0 0.301467 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::0 1855297 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 1855297 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1555651 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 8416980869 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048689 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 299646 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235741498 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 8981.209245 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 8.877118 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 83266 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 747829369 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses::0 15452577 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 15452577 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 26522.535484 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 23929.957773 # average overall mshr miss latency
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system.cpu.dcache.demand_hits::0 12022139 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 12022139 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 90983913582 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::0 0.221998 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.dcache.demand_misses::0 3430438 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 3430438 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2046935 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 33107168369 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::0 0.089532 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1383503 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 511.995488 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses::0 15452577 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 15452577 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::0 26522.535484 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 23929.957773 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits::0 12022139 # number of overall hits
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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system.cpu.dcache.overall_hits::total 12022139 # number of overall hits
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system.cpu.dcache.overall_miss_latency 90983913582 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate::0 0.221998 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.dcache.overall_misses::0 3430438 # number of overall misses
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
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system.cpu.dcache.overall_misses::total 3430438 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2046935 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 33107168369 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate::0 0.089532 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1383503 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 2141743498 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 1400321 # number of replacements
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system.cpu.dcache.sampled_refs 1400833 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 511.995488 # Cycle average of tags in use
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system.cpu.dcache.total_refs 12435360 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 832778 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 37796755 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 42128 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 613699 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 71391245 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 37490796 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 12847951 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 1515207 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 134411 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 1084532 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 1236239 # DTB accesses
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system.cpu.dtb.data_acv 812 # DTB access violations
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system.cpu.dtb.data_hits 16594781 # DTB hits
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system.cpu.dtb.data_misses 46795 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 911340 # DTB read accesses
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system.cpu.dtb.read_acv 579 # DTB read access violations
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system.cpu.dtb.read_hits 10007690 # DTB read hits
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system.cpu.dtb.read_misses 38589 # DTB read misses
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system.cpu.dtb.write_accesses 324899 # DTB write accesses
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system.cpu.dtb.write_acv 233 # DTB write access violations
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system.cpu.dtb.write_hits 6587091 # DTB write hits
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system.cpu.dtb.write_misses 8206 # DTB write misses
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system.cpu.fetch.Branches 14337786 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 8855787 # Number of cache lines fetched
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system.cpu.fetch.Cycles 23008954 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 454021 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 72656034 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 2787 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 884311 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.114667 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 8855787 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 7638352 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.581069 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 90735242 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.800748 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.110037 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 76622057 84.45% 84.45% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 1044700 1.15% 85.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 1968700 2.17% 87.77% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 923179 1.02% 88.78% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 2984209 3.29% 92.07% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 647959 0.71% 92.79% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 776741 0.86% 93.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1074256 1.18% 94.83% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 4693441 5.17% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 90735242 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.icache.ReadReq_accesses::0 8855787 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 8855787 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_avg_miss_latency::0 14954.156504 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.651524 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_hits::0 7815574 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 7815574 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_miss_latency 15555508000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.117461 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_misses::0 1040213 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1040213 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_mshr_hits 47670 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 11849625000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112078 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_misses 992543 # number of ReadReq MSHR misses
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 12375 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_refs 7.875775 # Average number of references to valid blocks.
|
|
system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_mshrs 693000 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.demand_accesses::0 8855787 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 8855787 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_avg_miss_latency::0 14954.156504 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11938.651524 # average overall mshr miss latency
|
|
system.cpu.icache.demand_hits::0 7815574 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 7815574 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_miss_latency 15555508000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_rate::0 0.117461 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.icache.demand_misses::0 1040213 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1040213 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_mshr_hits 47670 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_miss_latency 11849625000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.112078 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_misses 992543 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.occ_%::0 0.995724 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_blocks::0 509.810496 # Average occupied blocks per context
|
|
system.cpu.icache.overall_accesses::0 8855787 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 8855787 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_avg_miss_latency::0 14954.156504 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11938.651524 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_hits::0 7815574 # number of overall hits
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 7815574 # number of overall hits
|
|
system.cpu.icache.overall_miss_latency 15555508000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_rate::0 0.117461 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.icache.overall_misses::0 1040213 # number of overall misses
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1040213 # number of overall misses
|
|
system.cpu.icache.overall_mshr_hits 47670 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency 11849625000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.112078 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses 992543 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.replacements 991845 # number of replacements
|
|
system.cpu.icache.sampled_refs 992356 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 509.810496 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 7815573 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 24432989000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 92 # number of writebacks
|
|
system.cpu.idleCycles 34303252 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches 9120523 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop 3586903 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 0.457009 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 16684584 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 6610209 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 35266489 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 56698013 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 0.757126 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 26701175 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 0.453444 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 56800066 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 837864 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 9247048 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 10627556 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1790217 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 887680 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 6942367 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 65072200 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 10074375 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 520995 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 57143757 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 61290 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 11719 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 1515207 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 557918 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 132136 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 439501 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 9711 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 42523 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 17618 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1520348 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 553290 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 42523 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 405909 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 431955 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.424281 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.424281 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 39528092 68.55% 68.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 62364 0.11% 68.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.71% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.71% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.71% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.71% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 10425722 18.08% 86.80% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659174 11.55% 98.35% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 952878 1.65% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::total 57664754 # Type of FU issued
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 434083 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.007528 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 49311 11.36% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.36% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 268240 61.79% 73.15% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 116532 26.85% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 90735242 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635528 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200743 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 62361011 68.73% 68.73% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 14057815 15.49% 84.22% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 6222317 6.86% 91.08% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 3820698 4.21% 95.29% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 2539136 2.80% 98.09% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 1090667 1.20% 99.29% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 464211 0.51% 99.80% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 130030 0.14% 99.95% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 49357 0.05% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 90735242 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:rate 0.461176 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 59445556 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 57664754 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 2039741 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 8057348 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 28990 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1372161 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 4163419 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.fetch_accesses 1294712 # ITB accesses
|
|
system.cpu.itb.fetch_acv 931 # ITB acv
|
|
system.cpu.itb.fetch_hits 1255658 # ITB hits
|
|
system.cpu.itb.fetch_misses 39054 # ITB misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175584 91.19% 93.39% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5222 2.71% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 192554 # number of callpals executed
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.hwrei 211714 # number of hwrei instructions executed
|
|
system.cpu.kern.inst.quiesce 6425 # number of quiesce instructions executed
|
|
system.cpu.kern.ipl_count::0 74913 40.95% 40.95% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 242 0.13% 41.08% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105891 57.88% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182935 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73546 49.28% 49.28% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 242 0.16% 49.45% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73549 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 149226 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1826194246000 97.88% 97.88% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 98158000 0.01% 97.89% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 391805000 0.02% 97.91% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 39040113000 2.09% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1865724322000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.694573 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.mode_good::kernel 1907
|
|
system.cpu.kern.mode_good::user 1737
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch::kernel 5963 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches
|
|
system.cpu.kern.mode_switch_good::kernel 0.319805 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 1.400566 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 30090318500 1.61% 1.61% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 2984804000 0.16% 1.77% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1832649191500 98.23% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.memDep0.conflictingLoads 3016554 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2589214 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 10627556 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 6942367 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.numCycles 125038494 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 13289726 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 38227615 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 1062967 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 39056171 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1660859 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 58584 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 82207964 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 67568741 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 45291881 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 12513158 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 1515207 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 4651851 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 7064264 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 19709127 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 1694237 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 11738316 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 247282 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 1310688 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::1 137727.806267 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency 85724.248652 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_miss_latency 5722865806 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_mshr_miss_latency 3562013980 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
|
system.iocache.avg_blocked_cycles::no_mshrs 6169.439863 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_mshrs 64631052 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::1 137634.602852 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency 85631.059988 # average overall mshr miss latency
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
system.iocache.demand_miss_latency 5742803804 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.demand_mshr_miss_latency 3572955978 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.occ_%::1 0.081046 # Average percentage of cache occupancy
|
|
system.iocache.occ_blocks::1 1.296742 # Average occupied blocks per context
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::1 137634.602852 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency 85631.059988 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
system.iocache.overall_miss_latency 5742803804 # number of overall miss cycles
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
system.iocache.overall_misses::1 41725 # number of overall misses
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.overall_mshr_miss_latency 3572955978 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.replacements 41685 # number of replacements
|
|
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.tagsinuse 1.296742 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.warmup_cycle 1711281439000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks 41512 # number of writebacks
|
|
system.l2c.ReadExReq_accesses::0 300867 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 300867 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_avg_miss_latency::0 52486.783520 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40337.693248 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_hits::0 183854 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 183854 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_miss_latency 6141636000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_rate::0 0.388919 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses::0 117013 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 117013 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_mshr_miss_latency 4720034500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 0.388919 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_misses 117013 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadReq_accesses::0 2092394 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2092394 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_avg_miss_latency::0 52046.378325 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40015.178174 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_hits::0 1784912 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1784912 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_latency 16003324500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_rate::0 0.146952 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses::0 307482 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 307482 # number of ReadReq misses
|
|
system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_miss_latency 12303907000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.146952 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_misses 307481 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 811370500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.SCUpgradeReq_accesses::0 3 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
|
|
system.l2c.UpgradeReq_accesses::0 25 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 21400 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 44000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_hits::0 10 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 10 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_miss_latency 321000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_rate::0 0.600000 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses::0 15 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 15 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency 660000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 0.600000 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1116153998 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.Writeback_accesses::0 832870 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 832870 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits::0 832870 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 832870 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 5.629899 # Average number of references to valid blocks.
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses::0 2393261 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2393261 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency::0 52167.777006 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40104.080387 # average overall mshr miss latency
|
|
system.l2c.demand_hits::0 1968766 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1968766 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 22144960500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate::0 0.177371 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.l2c.demand_misses::0 424495 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 424495 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 17023941500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate::0 0.177371 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 424494 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.occ_%::0 0.186894 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::1 0.344697 # Average percentage of cache occupancy
|
|
system.l2c.occ_blocks::0 12248.264673 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::1 22590.041641 # Average occupied blocks per context
|
|
system.l2c.overall_accesses::0 2393261 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2393261 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency::0 52167.777006 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40104.080387 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits::0 1968766 # number of overall hits
|
|
system.l2c.overall_hits::1 0 # number of overall hits
|
|
system.l2c.overall_hits::total 1968766 # number of overall hits
|
|
system.l2c.overall_miss_latency 22144960500 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate::0 0.177371 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.l2c.overall_misses::0 424495 # number of overall misses
|
|
system.l2c.overall_misses::1 0 # number of overall misses
|
|
system.l2c.overall_misses::total 424495 # number of overall misses
|
|
system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 17023941500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate::0 0.177371 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 424494 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 1927524498 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 390994 # number of replacements
|
|
system.l2c.sampled_refs 423736 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 34838.306314 # Cycle average of tags in use
|
|
system.l2c.total_refs 2385591 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 5637119000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 117624 # number of writebacks
|
|
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
---------- End Simulation Statistics ----------
|