90b087171b
This patch breaks out the most basic configuration options into a set of base options, to allow them to be used also by scripts that do not involve any ISA, and thus no actual CPUs or devices. The patch also fixes a few modules so that they can be imported in a NULL build, and avoid dragging in FSConfig every time Options is imported.
186 lines
6.3 KiB
Python
186 lines
6.3 KiB
Python
#
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# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# For use for simulation and test purposes only
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its contributors
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# may be used to endorse or promote products derived from this software
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# without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Brad Beckmann
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#
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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addToPath('../')
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from common import Options
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from ruby import Ruby
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# Get paths we might need.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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parser = optparse.OptionParser()
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Options.addNoISAOptions(parser)
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parser.add_option("--maxloads", metavar="N", default=100,
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help="Stop after N loads")
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parser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
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help="Wakeup every N cycles")
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parser.add_option("-u", "--num-compute-units", type="int", default=1,
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help="number of compute units in the GPU")
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parser.add_option("--num-cp", type="int", default=0,
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help="Number of GPU Command Processors (CP)")
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# not super important now, but to avoid putting the number 4 everywhere, make
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# it an option/knob
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parser.add_option("--cu-per-sqc", type="int", default=4, help="number of CUs \
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sharing an SQC (icache, and thus icache TLB)")
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parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \
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"per CU")
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parser.add_option("--wf-size", type="int", default=64,
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help="Wavefront size(in workitems)")
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parser.add_option("--wfs-per-simd", type="int", default=10, help="Number of " \
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"WF slots per SIMD")
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#
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# Add the ruby specific and protocol specific options
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#
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Ruby.define_options(parser)
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execfile(os.path.join(config_root, "common", "Options.py"))
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(options, args) = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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options.l1d_size="256B"
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options.l1i_size="256B"
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options.l2_size="512B"
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options.l3_size="1kB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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# This file can support multiple compute units
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assert(options.num_compute_units >= 1)
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n_cu = options.num_compute_units
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options.num_sqc = int((n_cu + options.cu_per_sqc - 1) / options.cu_per_sqc)
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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#
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# Create the ruby random tester
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#
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# Check to for the GPU_RfO protocol. Other GPU protocols are non-SC and will
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# not work with the Ruby random tester.
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assert(buildEnv['PROTOCOL'] == 'GPU_RfO')
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# The GPU_RfO protocol does not support cache flushes
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check_flush = False
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tester = RubyTester(check_flush=check_flush,
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checks_to_complete=options.maxloads,
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wakeup_frequency=options.wakeup_freq,
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deadlock_threshold=1000000)
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#
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# Create the M5 system. Note that the Memory Object isn't
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# actually used by the rubytester, but is included to support the
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# M5 memory size == Ruby memory size checks
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#
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system = System(cpu=tester, mem_ranges=[AddrRange(options.mem_size)])
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# Create a top-level voltage domain and clock domain
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system.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
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system.clk_domain = SrcClockDomain(clock=options.sys_clock,
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voltage_domain=system.voltage_domain)
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Ruby.create_system(options, False, system)
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# Create a seperate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(clock=options.ruby_clock,
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voltage_domain=system.voltage_domain)
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tester.num_cpus = len(system.ruby._cpu_ports)
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#
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# The tester is most effective when randomization is turned on and
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# artifical delay is randomly inserted on messages
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#
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system.ruby.randomization = True
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for ruby_port in system.ruby._cpu_ports:
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#
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# Tie the ruby tester ports to the ruby cpu read and write ports
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#
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if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
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tester.cpuInstDataPort = ruby_port.slave
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elif ruby_port.support_data_reqs:
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tester.cpuDataPort = ruby_port.slave
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elif ruby_port.support_inst_reqs:
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tester.cpuInstPort = ruby_port.slave
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# Do not automatically retry stalled Ruby requests
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ruby_port.no_retry_on_stall = True
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#
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# Tell each sequencer this is the ruby tester so that it
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# copies the subblock back to the checker
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#
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ruby_port.using_ruby_tester = True
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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# instantiate configuration
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m5.instantiate()
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# simulate until program terminates
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exit_event = m5.simulate(options.abs_max_tick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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