438 lines
47 KiB
Text
438 lines
47 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 181883102 # Number of BTB hits
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global.BPredUnit.BTBLookups 205056000 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 84375502 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 253548806 # Number of conditional branches predicted
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global.BPredUnit.lookups 253548806 # Number of BP lookups
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global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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host_inst_rate 60603 # Simulator instruction rate (inst/s)
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host_mem_usage 181372 # Number of bytes of host memory used
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host_seconds 23193.76 # Real time elapsed on the host
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host_tick_rate 47543564 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 445533165 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 138523488 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 741821167 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 303434180 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1405610550 # Number of instructions simulated
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sim_seconds 1.102714 # Number of seconds simulated
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sim_ticks 1102714100000 # Number of ticks simulated
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system.cpu.commit.COM:branches 86246390 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 8144258 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 1965947566
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 1089819992 5543.48%
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1 575192807 2925.78%
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2 120683737 613.87%
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3 121997081 620.55%
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4 27903521 141.93%
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5 7399306 37.64%
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6 10435277 53.08%
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7 4371587 22.24%
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8 8144258 41.43%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 1489528973 # Number of instructions committed
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system.cpu.commit.COM:loads 402516086 # Number of loads committed
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system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
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system.cpu.commit.COM:refs 569373868 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 84375502 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 1379622895 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1405610550 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated
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system.cpu.cpi 1.569018 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.569018 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 431513840 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 5832.966573 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.823732 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 430676780 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4882543000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.001940 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 837060 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 610037 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 676261500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 6037.500000 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
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system.cpu.dcache.SwapReq_miss_latency 361500 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
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system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 166856456 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 10313.606533 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.204206 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 164722312 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 22010721500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.012790 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2134144 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1792165 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2651775000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.002050 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 341979 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 1192.980326 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 598370296 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 9051.301930 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 595399092 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 26893264500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.004965 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2971204 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2402202 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 3328036500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000951 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 569002 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 598370296 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 9051.301930 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 595399092 # number of overall hits
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system.cpu.dcache.overall_miss_latency 26893264500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.004965 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2971204 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2402202 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 3328036500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000951 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 569002 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 495151 # number of replacements
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system.cpu.dcache.sampled_refs 499247 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.753267 # Cycle average of tags in use
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system.cpu.dcache.total_refs 595591849 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 85544000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 338813 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 411958316 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:DecodedInsts 3446272352 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 768408181 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 782722330 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 239479384 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:UnblockCycles 2858739 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 253548806 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 356679455 # Number of cache lines fetched
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system.cpu.fetch.Cycles 1203440686 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 10248277 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 3739797008 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 90313792 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.114966 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 356679455 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 181883102 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.695724 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 2205426950
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system.cpu.fetch.rateDist.min_value 0
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0 1358665764 6160.56%
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1 256941668 1165.04%
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2 81115553 367.80%
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3 38329197 173.79%
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4 87812032 398.16%
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5 41184299 186.74%
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6 30948569 140.33%
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7 20663338 93.69%
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8 289766530 1313.88%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 356679455 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 8992.990654 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 6465.262380 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 356677957 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 13471500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 1498 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 145 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 8747500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 1353 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 263620.071693 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 356679455 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 8992.990654 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency
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system.cpu.icache.demand_hits 356677957 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 13471500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
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system.cpu.icache.demand_misses 1498 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 145 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 8747500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 1353 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 356679455 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 8992.990654 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 356677957 # number of overall hits
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system.cpu.icache.overall_miss_latency 13471500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
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system.cpu.icache.overall_misses 1498 # number of overall misses
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system.cpu.icache.overall_mshr_hits 145 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 8747500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 1353 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 208 # number of replacements
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system.cpu.icache.sampled_refs 1353 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1040.462476 # Cycle average of tags in use
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system.cpu.icache.total_refs 356677957 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 1251 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 127605912 # Number of branches executed
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system.cpu.iew.EXEC:nop 350340512 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.854314 # Inst execution rate
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system.cpu.iew.EXEC:refs 751911003 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 205327510 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 1480058841 # num instructions consuming a value
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system.cpu.iew.WB:count 1846013592 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.961975 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 1423779046 # num instructions producing a value
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system.cpu.iew.WB:rate 0.837032 # insts written-back per cycle
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system.cpu.iew.WB:sent 1859125771 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 92169328 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 589466 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 741821167 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 21373722 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 17131490 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 303434180 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 2869215575 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 546583493 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 102562223 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 1884127631 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 34476 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 6237 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 239479384 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 64949 # Number of cycles IEW is unblocking
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|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 115050739 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 46193 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 6187227 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 339305081 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 136576398 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 6187227 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 1512324 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 90657004 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.637341 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.637341 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 1986689854 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 0 0.00% # Type of FU issued
|
|
IntAlu 1179867838 59.39% # Type of FU issued
|
|
IntMult 0 0.00% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 3034528 0.15% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 573302529 28.86% # Type of FU issued
|
|
MemWrite 230484959 11.60% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 3941211 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.001984 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 143231 3.63% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 224126 5.69% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 3231195 81.98% # attempts to use FU when none available
|
|
MemWrite 342659 8.69% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 2205426950
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 1088269781 4934.51%
|
|
1 585554812 2655.06%
|
|
2 294018661 1333.16%
|
|
3 167298864 758.58%
|
|
4 47518780 215.46%
|
|
5 16542191 75.01%
|
|
6 5287334 23.97%
|
|
7 801167 3.63%
|
|
8 135360 0.61%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 0.900818 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 2497204504 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 1986689854 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 21670559 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 1069656656 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 613177 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 19427058 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 1294993594 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.l2cache.ReadExReq_accesses 272224 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 5810.711032 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2810.711032 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1581815000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 272224 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 765143000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 272224 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 228376 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 5108.225294 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2108.225294 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 193435 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 178486500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.152998 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 34941 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 73663500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.152998 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 34941 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 69802 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5210.366465 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2210.524054 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 363694000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 69802 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154299000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 69802 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 338813 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 338813 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 3.927611 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 500600 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 5730.801035 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 193435 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 1760301500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.613594 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 307165 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 838806500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.613594 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 307165 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 500600 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 5730.801035 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 193435 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 1760301500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.613594 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 307165 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 838806500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.613594 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 307165 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 84439 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 99904 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 16410.322643 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 392384 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 61955 # number of writebacks
|
|
system.cpu.numCycles 2205428201 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 14473307 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:FullRegisterEvents 14 # Number of times there has been no free registers
|
|
system.cpu.rename.RENAME:IQFullEvents 33045 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 831088395 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 23088197 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 4934346294 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 3102230072 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 2427283324 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 719527974 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 239479384 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 32278343 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 1182512267 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 368579547 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 22008768 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 170264872 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 21765105 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 5236 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|