b64eae5e52
SConscript: Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc. arch/alpha/isa_traits.hh: Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks(). cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: Replaced htoa()s with gtoh() and htog(). cpu/o3/fetch_impl.hh: cpu/simple/cpu.cc: Replaced htoa() with gtoh(). dev/disk_image.cc: Replaced htoa()s with letoh()s. dev/ide_ctrl.cc: Got rid of magic numbers. Added IdeChannel and IdeRegType type names where necessary. dev/ide_ctrl.hh: Got rid of unnecessary macros. Changed RegType_t to IdeRegType. Changed bmi_regs to allow accessing registers by name instead of just by array index. Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel. dev/ide_disk.cc: Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array. dev/ide_disk.hh: Updated command register struct. dev/ns_gige.cc: dev/ns_gige.hh: Made ReadConfig and WriteConfig begin with a lower-case letter. writeConfig() now takes a pointer to data as a parameter instead of a copy of data. dev/pciconfigall.cc: writeConfig() now takes a pointer to data as a parameter instead of a copy of data. dev/pcidev.cc: Cleaned up readConfig() and writeConfig() functions. dev/pcidev.hh: Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data. dev/pcireg.h: Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used. dev/rtcreg.h: Added macros for bit fields in RTC status registers A & B. dev/sinic.cc: Function name change: WriteConfig --> writeConfig. writeConfig() now takes a pointer to data instead of a copy of data. The accessing of elements of PCIConfig structure is updated. dev/sinic.hh: Function name change: WriteConfig --> writeConfig. writeConfig() now takes a pointer to data instead of a copy of data. dev/tsunami_io.cc: Added implementation of new RTC and PIT classes. dev/tsunami_io.hh: Added classes for RTC and PIT modules. dev/tsunamireg.h: Added macros for DMA ports used by Tsunami-Tru64. dev/uart8250.cc: Got rid of a magic number. Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register. dev/uart8250.hh: Added comments and macros dealing with the UART Interrupt ID register. kern/linux/linux_system.cc: Replaced htoa() with htog(). python/m5/objects/Pci.py: PciFake is a python class for Pci Devices that do nothing. python/m5/objects/Tsunami.py: TsunamiFake was renamed as IsaFake. sim/system.cc: Replaced htoa()s with htog()s. dev/isa_fake.cc: New BitKeeper file ``dev/isa_fake.cc'' TsunamiFake was renamed as IsaFake. dev/isa_fake.hh: New BitKeeper file ``dev/isa_fake.hh'' TsunmaiFake was renamed as IsaFake. dev/pitreg.h: New BitKeeper file ``dev/pitreg.h'' Useful macros for working with PIT (Periodic Interval Timer) registers. --HG-- extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
906 lines
24 KiB
C++
906 lines
24 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <cmath>
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#include <cstdio>
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#include <cstdlib>
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#include <iostream>
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#include <iomanip>
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#include <list>
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#include <sstream>
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#include <string>
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/pollevent.hh"
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#include "base/range.hh"
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#include "base/stats/events.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/sampler/sampler.hh"
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#include "cpu/simple/cpu.hh"
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#include "cpu/smt.hh"
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#include "cpu/static_inst.hh"
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#include "mem/base_mem.hh"
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#include "mem/mem_interface.hh"
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#include "sim/builder.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#ifdef FULL_SYSTEM
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#include "base/remote_gdb.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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#include "sim/system.hh"
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#include "targetarch/alpha_memory.hh"
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#include "targetarch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "mem/functional/functional.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
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{
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}
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void
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SimpleCPU::TickEvent::process()
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{
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int count = width;
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do {
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cpu->tick();
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} while (--count > 0 && cpu->status() == Running);
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}
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const char *
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SimpleCPU::TickEvent::description()
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{
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return "SimpleCPU tick event";
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}
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SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
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: Event(&mainEventQueue), cpu(_cpu)
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{
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}
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void SimpleCPU::CacheCompletionEvent::process()
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{
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cpu->processCacheCompletion();
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}
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const char *
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SimpleCPU::CacheCompletionEvent::description()
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{
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return "SimpleCPU cache completion event";
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}
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SimpleCPU::SimpleCPU(Params *p)
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: BaseCPU(p), tickEvent(this, p->width), xc(NULL),
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cacheCompletionEvent(this)
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{
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_status = Idle;
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#ifdef FULL_SYSTEM
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xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
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// initialize CPU, including PC
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TheISA::initCPU(&xc->regs);
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#else
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xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
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#endif // !FULL_SYSTEM
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icacheInterface = p->icache_interface;
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dcacheInterface = p->dcache_interface;
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memReq = new MemReq();
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memReq->xc = xc;
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memReq->asid = 0;
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memReq->data = new uint8_t[64];
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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lastIcacheStall = 0;
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lastDcacheStall = 0;
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execContexts.push_back(xc);
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}
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SimpleCPU::~SimpleCPU()
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{
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}
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void
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SimpleCPU::switchOut(Sampler *s)
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{
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sampler = s;
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if (status() == DcacheMissStall) {
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DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n");
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_status = DcacheMissSwitch;
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}
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else {
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_status = SwitchedOut;
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if (tickEvent.scheduled())
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tickEvent.squash();
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sampler->signalSwitched();
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}
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}
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void
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SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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assert(!tickEvent.scheduled());
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// if any of this CPU's ExecContexts are active, mark the CPU as
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// running and schedule its tick event.
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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if (xc->status() == ExecContext::Active && _status != Running) {
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_status = Running;
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tickEvent.schedule(curTick);
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}
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}
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}
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void
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SimpleCPU::activateContext(int thread_num, int delay)
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{
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assert(thread_num == 0);
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assert(xc);
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assert(_status == Idle);
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notIdleFraction++;
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scheduleTickEvent(delay);
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_status = Running;
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}
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void
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SimpleCPU::suspendContext(int thread_num)
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{
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assert(thread_num == 0);
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assert(xc);
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assert(_status == Running);
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notIdleFraction--;
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unscheduleTickEvent();
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_status = Idle;
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}
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void
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SimpleCPU::deallocateContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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SimpleCPU::haltContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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SimpleCPU::regStats()
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{
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using namespace Stats;
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BaseCPU::regStats();
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numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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numMemRefs
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.name(name() + ".num_refs")
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.desc("Number of memory references")
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;
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notIdleFraction
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.name(name() + ".not_idle_fraction")
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.desc("Percentage of non-idle cycles")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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icacheStallCycles
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.name(name() + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(icacheStallCycles)
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;
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dcacheStallCycles
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.name(name() + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(dcacheStallCycles)
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;
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idleFraction = constant(1.0) - notIdleFraction;
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}
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void
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SimpleCPU::resetStats()
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{
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startNumInst = numInst;
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notIdleFraction = (_status != Idle);
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}
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void
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SimpleCPU::serialize(ostream &os)
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{
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BaseCPU::serialize(os);
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SERIALIZE_ENUM(_status);
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SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc", name()));
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xc->serialize(os);
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
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cacheCompletionEvent.serialize(os);
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}
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void
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SimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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BaseCPU::unserialize(cp, section);
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UNSERIALIZE_ENUM(_status);
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UNSERIALIZE_SCALAR(inst);
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xc->unserialize(cp, csprintf("%s.xc", section));
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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cacheCompletionEvent
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.unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
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}
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void
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change_thread_state(int thread_number, int activate, int priority)
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{
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}
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Fault
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SimpleCPU::copySrcTranslate(Addr src)
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{
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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int offset = src & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
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(src >> 40) != 0xfffffc) {
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warn("Copied block source spans pages %x.", src);
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no_warn = false;
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}
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memReq->reset(src & ~(blk_size - 1), blk_size);
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// translate to physical address
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Fault fault = xc->translateDataReadReq(memReq);
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assert(fault != Alignment_Fault);
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if (fault == No_Fault) {
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xc->copySrcAddr = src;
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xc->copySrcPhysAddr = memReq->paddr + offset;
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} else {
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xc->copySrcAddr = 0;
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xc->copySrcPhysAddr = 0;
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}
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return fault;
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}
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Fault
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SimpleCPU::copy(Addr dest)
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{
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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uint8_t data[blk_size];
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//assert(xc->copySrcAddr);
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int offset = dest & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
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(dest >> 40) != 0xfffffc) {
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no_warn = false;
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warn("Copied block destination spans pages %x. ", dest);
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}
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memReq->reset(dest & ~(blk_size -1), blk_size);
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// translate to physical address
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Fault fault = xc->translateDataWriteReq(memReq);
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assert(fault != Alignment_Fault);
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if (fault == No_Fault) {
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Addr dest_addr = memReq->paddr + offset;
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// Need to read straight from memory since we have more than 8 bytes.
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memReq->paddr = xc->copySrcPhysAddr;
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xc->mem->read(memReq, data);
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memReq->paddr = dest_addr;
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xc->mem->write(memReq, data);
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if (dcacheInterface) {
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memReq->cmd = Copy;
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memReq->completionEvent = NULL;
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memReq->paddr = xc->copySrcPhysAddr;
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memReq->dest = dest_addr;
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memReq->size = 64;
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memReq->time = curTick;
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dcacheInterface->access(memReq);
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}
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}
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return fault;
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}
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// precise architected memory state accessor macros
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template <class T>
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Fault
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SimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
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Fault fault = xc->read(memReq,data);
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if (traceData) {
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traceData->setAddr(addr);
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}
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return fault;
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}
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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Fault fault = xc->translateDataReadReq(memReq);
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// if we have a cache, do cache access too
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if (fault == No_Fault && dcacheInterface) {
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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memReq->completionEvent = &cacheCompletionEvent;
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lastDcacheStall = curTick;
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unscheduleTickEvent();
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_status = DcacheMissStall;
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} else {
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// do functional access
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fault = xc->read(memReq, data);
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}
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} else if(fault == No_Fault) {
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// do functional access
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fault = xc->read(memReq, data);
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}
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if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
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recordEvent("Uncached Read");
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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SimpleCPU::read(Addr addr, double &data, unsigned flags)
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{
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return read(addr, *(uint64_t*)&data, flags);
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}
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template<>
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Fault
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SimpleCPU::read(Addr addr, float &data, unsigned flags)
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{
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
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{
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return read(addr, (uint32_t&)data, flags);
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}
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template <class T>
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Fault
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SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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Fault fault = xc->translateDataWriteReq(memReq);
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// do functional access
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if (fault == No_Fault)
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fault = xc->write(memReq, data);
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if (fault == No_Fault && dcacheInterface) {
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memReq->cmd = Write;
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memcpy(memReq->data,(uint8_t *)&data,memReq->size);
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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|
if (result != MA_HIT && dcacheInterface->doEvents()) {
|
|
memReq->completionEvent = &cacheCompletionEvent;
|
|
lastDcacheStall = curTick;
|
|
unscheduleTickEvent();
|
|
_status = DcacheMissStall;
|
|
}
|
|
}
|
|
|
|
if (res && (fault == No_Fault))
|
|
*res = memReq->result;
|
|
|
|
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
|
|
recordEvent("Uncached Write");
|
|
|
|
return fault;
|
|
}
|
|
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
return write(*(uint64_t*)&data, addr, flags, res);
|
|
}
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
return write(*(uint32_t*)&data, addr, flags, res);
|
|
}
|
|
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
return write((uint32_t)data, addr, flags, res);
|
|
}
|
|
|
|
|
|
#ifdef FULL_SYSTEM
|
|
Addr
|
|
SimpleCPU::dbg_vtophys(Addr addr)
|
|
{
|
|
return vtophys(xc, addr);
|
|
}
|
|
#endif // FULL_SYSTEM
|
|
|
|
void
|
|
SimpleCPU::processCacheCompletion()
|
|
{
|
|
switch (status()) {
|
|
case IcacheMissStall:
|
|
icacheStallCycles += curTick - lastIcacheStall;
|
|
_status = IcacheMissComplete;
|
|
scheduleTickEvent(1);
|
|
break;
|
|
case DcacheMissStall:
|
|
if (memReq->cmd.isRead()) {
|
|
curStaticInst->execute(this,traceData);
|
|
if (traceData)
|
|
traceData->finalize();
|
|
}
|
|
dcacheStallCycles += curTick - lastDcacheStall;
|
|
_status = Running;
|
|
scheduleTickEvent(1);
|
|
break;
|
|
case DcacheMissSwitch:
|
|
if (memReq->cmd.isRead()) {
|
|
curStaticInst->execute(this,traceData);
|
|
if (traceData)
|
|
traceData->finalize();
|
|
}
|
|
_status = SwitchedOut;
|
|
sampler->signalSwitched();
|
|
case SwitchedOut:
|
|
// If this CPU has been switched out due to sampling/warm-up,
|
|
// ignore any further status changes (e.g., due to cache
|
|
// misses outstanding at the time of the switch).
|
|
return;
|
|
default:
|
|
panic("SimpleCPU::processCacheCompletion: bad state");
|
|
break;
|
|
}
|
|
}
|
|
|
|
#ifdef FULL_SYSTEM
|
|
void
|
|
SimpleCPU::post_interrupt(int int_num, int index)
|
|
{
|
|
BaseCPU::post_interrupt(int_num, index);
|
|
|
|
if (xc->status() == ExecContext::Suspended) {
|
|
DPRINTF(IPI,"Suspended Processor awoke\n");
|
|
xc->activate();
|
|
}
|
|
}
|
|
#endif // FULL_SYSTEM
|
|
|
|
/* start simulation, program loaded, processor precise state initialized */
|
|
void
|
|
SimpleCPU::tick()
|
|
{
|
|
numCycles++;
|
|
|
|
traceData = NULL;
|
|
|
|
Fault fault = No_Fault;
|
|
|
|
#ifdef FULL_SYSTEM
|
|
if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
|
|
status() != IcacheMissComplete) {
|
|
int ipl = 0;
|
|
int summary = 0;
|
|
checkInterrupts = false;
|
|
IntReg *ipr = xc->regs.ipr;
|
|
|
|
if (xc->regs.ipr[TheISA::IPR_SIRR]) {
|
|
for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
|
|
i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
|
|
if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
|
|
// See table 4-19 of 21164 hardware reference
|
|
ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
}
|
|
|
|
uint64_t interrupts = xc->cpu->intr_status();
|
|
for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
|
|
i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
|
|
if (interrupts & (ULL(1) << i)) {
|
|
// See table 4-19 of 21164 hardware reference
|
|
ipl = i;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
|
|
if (ipr[TheISA::IPR_ASTRR])
|
|
panic("asynchronous traps not implemented\n");
|
|
|
|
if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
|
|
ipr[TheISA::IPR_ISR] = summary;
|
|
ipr[TheISA::IPR_INTID] = ipl;
|
|
xc->ev5_trap(Interrupt_Fault);
|
|
|
|
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
|
|
ipr[TheISA::IPR_IPLR], ipl, summary);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// maintain $r0 semantics
|
|
xc->regs.intRegFile[ZeroReg] = 0;
|
|
#ifdef TARGET_ALPHA
|
|
xc->regs.floatRegFile.d[ZeroReg] = 0.0;
|
|
#endif // TARGET_ALPHA
|
|
|
|
if (status() == IcacheMissComplete) {
|
|
// We've already fetched an instruction and were stalled on an
|
|
// I-cache miss. No need to fetch it again.
|
|
|
|
// Set status to running; tick event will get rescheduled if
|
|
// necessary at end of tick() function.
|
|
_status = Running;
|
|
}
|
|
else {
|
|
// Try to fetch an instruction
|
|
|
|
// set up memory request for instruction fetch
|
|
#ifdef FULL_SYSTEM
|
|
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
|
|
#else
|
|
#define IFETCH_FLAGS(pc) 0
|
|
#endif
|
|
|
|
memReq->cmd = Read;
|
|
memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
|
|
IFETCH_FLAGS(xc->regs.pc));
|
|
|
|
fault = xc->translateInstReq(memReq);
|
|
|
|
if (fault == No_Fault)
|
|
fault = xc->mem->read(memReq, inst);
|
|
|
|
if (icacheInterface && fault == No_Fault) {
|
|
memReq->completionEvent = NULL;
|
|
|
|
memReq->time = curTick;
|
|
MemAccessResult result = icacheInterface->access(memReq);
|
|
|
|
// Ugly hack to get an event scheduled *only* if the access is
|
|
// a miss. We really should add first-class support for this
|
|
// at some point.
|
|
if (result != MA_HIT && icacheInterface->doEvents()) {
|
|
memReq->completionEvent = &cacheCompletionEvent;
|
|
lastIcacheStall = curTick;
|
|
unscheduleTickEvent();
|
|
_status = IcacheMissStall;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
// If we've got a valid instruction (i.e., no fault on instruction
|
|
// fetch), then execute it.
|
|
if (fault == No_Fault) {
|
|
|
|
// keep an instruction count
|
|
numInst++;
|
|
numInsts++;
|
|
|
|
// check for instruction-count-based events
|
|
comInstEventQueue[0]->serviceEvents(numInst);
|
|
|
|
// decode the instruction
|
|
inst = gtoh(inst);
|
|
curStaticInst = StaticInst<TheISA>::decode(inst);
|
|
|
|
traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
|
|
xc->regs.pc);
|
|
|
|
#ifdef FULL_SYSTEM
|
|
xc->setInst(inst);
|
|
#endif // FULL_SYSTEM
|
|
|
|
xc->func_exe_inst++;
|
|
|
|
fault = curStaticInst->execute(this, traceData);
|
|
|
|
#ifdef FULL_SYSTEM
|
|
if (xc->fnbin)
|
|
xc->execute(curStaticInst.get());
|
|
#endif
|
|
|
|
if (curStaticInst->isMemRef()) {
|
|
numMemRefs++;
|
|
}
|
|
|
|
if (curStaticInst->isLoad()) {
|
|
++numLoad;
|
|
comLoadEventQueue[0]->serviceEvents(numLoad);
|
|
}
|
|
|
|
// If we have a dcache miss, then we can't finialize the instruction
|
|
// trace yet because we want to populate it with the data later
|
|
if (traceData &&
|
|
!(status() == DcacheMissStall && memReq->cmd.isRead())) {
|
|
traceData->finalize();
|
|
}
|
|
|
|
traceFunctions(xc->regs.pc);
|
|
|
|
} // if (fault == No_Fault)
|
|
|
|
if (fault != No_Fault) {
|
|
#ifdef FULL_SYSTEM
|
|
xc->ev5_trap(fault);
|
|
#else // !FULL_SYSTEM
|
|
fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
|
|
#endif // FULL_SYSTEM
|
|
}
|
|
else {
|
|
// go to the next instruction
|
|
xc->regs.pc = xc->regs.npc;
|
|
xc->regs.npc += sizeof(MachInst);
|
|
}
|
|
|
|
#ifdef FULL_SYSTEM
|
|
Addr oldpc;
|
|
do {
|
|
oldpc = xc->regs.pc;
|
|
system->pcEventQueue.service(xc);
|
|
} while (oldpc != xc->regs.pc);
|
|
#endif
|
|
|
|
assert(status() == Running ||
|
|
status() == Idle ||
|
|
status() == DcacheMissStall);
|
|
|
|
if (status() == Running && !tickEvent.scheduled())
|
|
tickEvent.schedule(curTick + cycles(1));
|
|
}
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// SimpleCPU Simulation Object
|
|
//
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
Param<Counter> max_insts_any_thread;
|
|
Param<Counter> max_insts_all_threads;
|
|
Param<Counter> max_loads_any_thread;
|
|
Param<Counter> max_loads_all_threads;
|
|
|
|
#ifdef FULL_SYSTEM
|
|
SimObjectParam<AlphaITB *> itb;
|
|
SimObjectParam<AlphaDTB *> dtb;
|
|
SimObjectParam<FunctionalMemory *> mem;
|
|
SimObjectParam<System *> system;
|
|
Param<int> cpu_id;
|
|
#else
|
|
SimObjectParam<Process *> workload;
|
|
#endif // FULL_SYSTEM
|
|
|
|
Param<int> clock;
|
|
SimObjectParam<BaseMem *> icache;
|
|
SimObjectParam<BaseMem *> dcache;
|
|
|
|
Param<bool> defer_registration;
|
|
Param<int> width;
|
|
Param<bool> function_trace;
|
|
Param<Tick> function_trace_start;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
INIT_PARAM(max_insts_any_thread,
|
|
"terminate when any thread reaches this inst count"),
|
|
INIT_PARAM(max_insts_all_threads,
|
|
"terminate when all threads have reached this inst count"),
|
|
INIT_PARAM(max_loads_any_thread,
|
|
"terminate when any thread reaches this load count"),
|
|
INIT_PARAM(max_loads_all_threads,
|
|
"terminate when all threads have reached this load count"),
|
|
|
|
#ifdef FULL_SYSTEM
|
|
INIT_PARAM(itb, "Instruction TLB"),
|
|
INIT_PARAM(dtb, "Data TLB"),
|
|
INIT_PARAM(mem, "memory"),
|
|
INIT_PARAM(system, "system object"),
|
|
INIT_PARAM(cpu_id, "processor ID"),
|
|
#else
|
|
INIT_PARAM(workload, "processes to run"),
|
|
#endif // FULL_SYSTEM
|
|
|
|
INIT_PARAM(clock, "clock speed"),
|
|
INIT_PARAM(icache, "L1 instruction cache object"),
|
|
INIT_PARAM(dcache, "L1 data cache object"),
|
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
|
INIT_PARAM(width, "cpu width"),
|
|
INIT_PARAM(function_trace, "Enable function trace"),
|
|
INIT_PARAM(function_trace_start, "Cycle to start function trace")
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
|
|
CREATE_SIM_OBJECT(SimpleCPU)
|
|
{
|
|
SimpleCPU::Params *params = new SimpleCPU::Params();
|
|
params->name = getInstanceName();
|
|
params->numberOfThreads = 1;
|
|
params->max_insts_any_thread = max_insts_any_thread;
|
|
params->max_insts_all_threads = max_insts_all_threads;
|
|
params->max_loads_any_thread = max_loads_any_thread;
|
|
params->max_loads_all_threads = max_loads_all_threads;
|
|
params->deferRegistration = defer_registration;
|
|
params->clock = clock;
|
|
params->functionTrace = function_trace;
|
|
params->functionTraceStart = function_trace_start;
|
|
params->icache_interface = (icache) ? icache->getInterface() : NULL;
|
|
params->dcache_interface = (dcache) ? dcache->getInterface() : NULL;
|
|
params->width = width;
|
|
|
|
#ifdef FULL_SYSTEM
|
|
params->itb = itb;
|
|
params->dtb = dtb;
|
|
params->mem = mem;
|
|
params->system = system;
|
|
params->cpu_id = cpu_id;
|
|
#else
|
|
params->process = workload;
|
|
#endif
|
|
|
|
SimpleCPU *cpu = new SimpleCPU(params);
|
|
return cpu;
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
|
|
|