c0b9f324bf
This patch updates the realview regressions stats to reflect that nvmem moved in the object hierarchy and is now under system.realview.
325 lines
36 KiB
Plaintext
325 lines
36 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.332317 # Number of seconds simulated
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sim_ticks 2332316587000 # Number of ticks simulated
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final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 2011652 # Simulator instruction rate (inst/s)
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host_op_rate 2597875 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 79169370264 # Simulator tick rate (ticks/s)
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host_mem_usage 376316 # Number of bytes of host memory used
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host_seconds 29.46 # Real time elapsed on the host
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sim_insts 59262876 # Number of instructions simulated
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sim_ops 76532931 # Number of ops (including micro ops) simulated
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system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
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system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
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system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
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system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_read 122663536 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 941280 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 9577800 # Number of bytes written to this memory
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system.physmem.num_reads 14137126 # Number of read requests responded to by this memory
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system.physmem.num_writes 856485 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.replacements 116822 # number of replacements
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system.l2c.tagsinuse 24240.388378 # Cycle average of tags in use
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system.l2c.total_refs 1520830 # Total number of references to valid blocks.
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system.l2c.sampled_refs 146847 # Sample count of references to valid blocks.
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system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::writebacks 13639.466210 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu.data 5344.680069 # Average occupied blocks per requestor
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system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu.inst 0.080054 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu.data 0.081553 # Average percentage of cache occupancy
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system.l2c.occ_percent::total 0.369879 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::cpu.dtb.walker 7522 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu.itb.walker 3147 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu.inst 831710 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu.data 356506 # number of ReadReq hits
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system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits
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system.l2c.Writeback_hits::writebacks 604613 # number of Writeback hits
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system.l2c.Writeback_hits::total 604613 # number of Writeback hits
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system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
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system.l2c.ReadExReq_hits::cpu.data 105791 # number of ReadExReq hits
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system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits
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system.l2c.demand_hits::cpu.dtb.walker 7522 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu.itb.walker 3147 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu.inst 831710 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu.data 462297 # number of demand (read+write) hits
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system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits
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system.l2c.overall_hits::cpu.dtb.walker 7522 # number of overall hits
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system.l2c.overall_hits::cpu.itb.walker 3147 # number of overall hits
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system.l2c.overall_hits::cpu.inst 831710 # number of overall hits
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system.l2c.overall_hits::cpu.data 462297 # number of overall hits
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system.l2c.overall_hits::total 1304676 # number of overall hits
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system.l2c.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu.inst 14294 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu.data 17422 # number of ReadReq misses
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system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses
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system.l2c.UpgradeReq_misses::cpu.data 2911 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses
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system.l2c.ReadExReq_misses::cpu.data 141169 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses
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system.l2c.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu.inst 14294 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu.data 158591 # number of demand (read+write) misses
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system.l2c.demand_misses::total 172912 # number of demand (read+write) misses
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system.l2c.overall_misses::cpu.dtb.walker 19 # number of overall misses
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system.l2c.overall_misses::cpu.itb.walker 8 # number of overall misses
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system.l2c.overall_misses::cpu.inst 14294 # number of overall misses
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system.l2c.overall_misses::cpu.data 158591 # number of overall misses
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system.l2c.overall_misses::total 172912 # number of overall misses
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system.l2c.ReadReq_accesses::cpu.dtb.walker 7541 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu.itb.walker 3155 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu.inst 846004 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu.data 373928 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses)
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system.l2c.Writeback_accesses::writebacks 604613 # number of Writeback accesses(hits+misses)
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system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::cpu.data 2937 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::cpu.data 246960 # number of ReadExReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses)
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system.l2c.demand_accesses::cpu.dtb.walker 7541 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu.itb.walker 3155 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu.inst 846004 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu.data 620888 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses
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system.l2c.overall_accesses::cpu.dtb.walker 7541 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu.itb.walker 3155 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu.inst 846004 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu.data 620888 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses
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system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002520 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.002536 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu.inst 0.016896 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::cpu.data 0.991147 # miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::cpu.data 0.571627 # miss rate for ReadExReq accesses
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system.l2c.demand_miss_rate::cpu.dtb.walker 0.002520 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu.itb.walker 0.002536 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu.inst 0.016896 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu.data 0.255426 # miss rate for demand accesses
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system.l2c.overall_miss_rate::cpu.dtb.walker 0.002520 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu.itb.walker 0.002536 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu.inst 0.016896 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu.data 0.255426 # miss rate for overall accesses
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.l2c.fast_writes 0 # number of fast writes performed
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system.l2c.cache_copies 0 # number of cache copies performed
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system.l2c.writebacks::writebacks 102531 # number of writebacks
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system.l2c.writebacks::total 102531 # number of writebacks
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 14940566 # DTB read hits
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system.cpu.dtb.read_misses 7288 # DTB read misses
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system.cpu.dtb.write_hits 11198205 # DTB write hits
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system.cpu.dtb.write_misses 2199 # DTB write misses
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 14947854 # DTB read accesses
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system.cpu.dtb.write_accesses 11200404 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 26138771 # DTB hits
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system.cpu.dtb.misses 9487 # DTB misses
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system.cpu.dtb.accesses 26148258 # DTB accesses
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system.cpu.itb.inst_hits 60273889 # ITB inst hits
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system.cpu.itb.inst_misses 4471 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 60278360 # ITB inst accesses
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system.cpu.itb.hits 60273889 # DTB hits
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system.cpu.itb.misses 4471 # DTB misses
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system.cpu.itb.accesses 60278360 # DTB accesses
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system.cpu.numCycles 4664556206 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 59262876 # Number of instructions committed
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system.cpu.committedOps 76532931 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
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system.cpu.num_func_calls 1971944 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 7572657 # number of instructions that are conditional controls
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system.cpu.num_int_insts 68161177 # number of integer instructions
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system.cpu.num_fp_insts 10269 # number of float instructions
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system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read
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system.cpu.num_int_register_writes 72877692 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
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system.cpu.num_mem_refs 27310784 # number of memory refs
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system.cpu.num_load_insts 15607074 # Number of load instructions
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system.cpu.num_store_insts 11703710 # Number of store instructions
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system.cpu.num_idle_cycles 4586920150.977920 # Number of idle cycles
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system.cpu.num_busy_cycles 77636055.022080 # Number of busy cycles
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system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0.983356 # Percentage of idle cycles
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
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system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed
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system.cpu.icache.replacements 847054 # number of replacements
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system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use
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system.cpu.icache.total_refs 59429083 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 59429083 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 59429083 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 59429083 # number of overall hits
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system.cpu.icache.overall_hits::total 59429083 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses
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system.cpu.icache.overall_misses::total 847566 # number of overall misses
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system.cpu.icache.ReadReq_accesses::cpu.inst 60276649 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 60276649 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 60276649 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks::writebacks 44721 # number of writebacks
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system.cpu.icache.writebacks::total 44721 # number of writebacks
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 622134 # number of replacements
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system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
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system.cpu.dcache.total_refs 23580069 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 13150366 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 9943631 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 23093997 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 23093997 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 23093997 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11138 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 614445 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 614445 # number of overall misses
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 13514914 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10193528 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 23708442 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 23708442 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.025917 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.025917 # miss rate for overall accesses
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 559892 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 559892 # number of writebacks
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|