133 lines
3.9 KiB
C++
133 lines
3.9 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Gabe Black
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*/
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#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
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#define __ARCH_ALPHA_ISA_TRAITS_HH__
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namespace LittleEndianGuest {}
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#include "arch/alpha/types.hh"
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#include "base/types.hh"
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#include "cpu/static_inst_fwd.hh"
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namespace AlphaISA {
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using namespace LittleEndianGuest;
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StaticInstPtr decodeInst(ExtMachInst);
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// Alpha Does NOT have a delay slot
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#define ISA_HAS_DELAY_SLOT 0
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const Addr PageShift = 13;
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const Addr PageBytes = ULL(1) << PageShift;
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const Addr PageMask = ~(PageBytes - 1);
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const Addr PageOffset = PageBytes - 1;
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////////////////////////////////////////////////////////////////////////
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//
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// Translation stuff
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//
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const Addr PteShift = 3;
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const Addr NPtePageShift = PageShift - PteShift;
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const Addr NPtePage = ULL(1) << NPtePageShift;
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const Addr PteMask = NPtePage - 1;
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// User Virtual
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const Addr USegBase = ULL(0x0);
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const Addr USegEnd = ULL(0x000003ffffffffff);
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// Kernel Direct Mapped
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const Addr K0SegBase = ULL(0xfffffc0000000000);
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const Addr K0SegEnd = ULL(0xfffffdffffffffff);
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// Kernel Virtual
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const Addr K1SegBase = ULL(0xfffffe0000000000);
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const Addr K1SegEnd = ULL(0xffffffffffffffff);
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////////////////////////////////////////////////////////////////////////
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//
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// Interrupt levels
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//
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enum InterruptLevels
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{
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INTLEVEL_SOFTWARE_MIN = 4,
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INTLEVEL_SOFTWARE_MAX = 19,
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INTLEVEL_EXTERNAL_MIN = 20,
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INTLEVEL_EXTERNAL_MAX = 34,
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INTLEVEL_IRQ0 = 20,
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INTLEVEL_IRQ1 = 21,
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INTINDEX_ETHERNET = 0,
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INTINDEX_SCSI = 1,
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INTLEVEL_IRQ2 = 22,
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INTLEVEL_IRQ3 = 23,
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INTLEVEL_SERIAL = 33,
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NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
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};
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// EV5 modes
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enum mode_type
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{
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mode_kernel = 0, // kernel
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mode_executive = 1, // executive (unused by unix)
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mode_supervisor = 2, // supervisor (unused by unix)
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mode_user = 3, // user mode
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mode_number // number of modes
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};
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// Constants Related to the number of registers
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enum {
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LogVMPageSize = 13, // 8K bytes
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VMPageSize = (1 << LogVMPageSize),
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BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
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MachineBytes = 8,
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WordBytes = 4,
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HalfwordBytes = 2,
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ByteBytes = 1
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};
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// return a no-op instruction... used for instruction fetch faults
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const extern StaticInstPtr NoopStaticInst;
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// Memory accesses cannot be unaligned
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const bool HasUnalignedMemAcc = false;
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} // namespace AlphaISA
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#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
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