936 lines
27 KiB
Text
936 lines
27 KiB
Text
Real time: Feb/02/2013 08:11:05
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Virtual_time_in_seconds: 0.51
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Virtual_time_in_minutes: 0.0085
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Virtual_time_in_hours: 0.000141667
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Virtual_time_in_days: 5.90278e-06
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Ruby_current_time: 35432
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Ruby_start_time: 0
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Ruby_cycles: 35432
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mbytes_resident: 51.3359
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mbytes_total: 266.984
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resident_ratio: 0.192325
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ruby_cycles_executed: [ 35433 ]
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Busy Controller Counts:
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L1Cache-0:0
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Directory-0:0
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Busy Bank Count:0
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sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 1 max: 122 count: 3294 average: 9.75653 | standard deviation: 19.3896 | 0 0 2784 0 0 0 0 0 0 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 327 37 9 38 4 1 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 2 1 8 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 ]
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miss_latency_LD: [binsize: 1 max: 122 count: 415 average: 22.8313 | standard deviation: 27.0523 | 0 0 233 0 0 0 0 0 0 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 110 14 1 9 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
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miss_latency_ST: [binsize: 1 max: 122 count: 294 average: 12.0102 | standard deviation: 23.154 | 0 0 236 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 0 2 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ]
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miss_latency_IFETCH: [binsize: 1 max: 83 count: 2585 average: 7.40116 | standard deviation: 16.3551 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 181 23 6 25 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 5 ]
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miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ]
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miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
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miss_latency_Directory: [binsize: 1 max: 122 count: 441 average: 58.2154 | standard deviation: 8.81927 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 327 37 9 38 4 1 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 2 1 8 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 ]
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_wCC_Times: 0
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miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
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miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
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imcomplete_dir_Times: 440
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miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
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miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
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miss_latency_LD_Directory: [binsize: 1 max: 122 count: 146 average: 58.5 | standard deviation: 9.33625 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 110 14 1 9 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
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miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ]
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miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
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miss_latency_ST_Directory: [binsize: 1 max: 122 count: 47 average: 62.0426 | standard deviation: 18.5144 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 0 2 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ]
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miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
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miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
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miss_latency_IFETCH_Directory: [binsize: 1 max: 83 count: 248 average: 57.3226 | standard deviation: 4.46262 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 181 23 6 25 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 5 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Request vs. RubySystem State Profile
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--------------------------------
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filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Message Delayed Cycles
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----------------------
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Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Resource Usage
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--------------
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 10808
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page_faults: 0
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swaps: 0
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block_inputs: 0
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block_outputs: 96
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Network Stats
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-------------
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total_msg_count_Request_Control: 1323 10584
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total_msg_count_Response_Data: 1323 95256
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total_msg_count_Writeback_Data: 243 17496
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total_msg_count_Writeback_Control: 3582 28656
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total_msg_count_Unblock_Control: 1320 10560
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total_msgs: 7791 total_bytes: 162552
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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links_utilized_percent_switch_0: 4.77887
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links_utilized_percent_switch_0_link_0: 6.20061 bw: 16000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 3.35713 bw: 16000 base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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links_utilized_percent_switch_1: 4.77887
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links_utilized_percent_switch_1_link_0: 3.35713 bw: 16000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 6.20061 bw: 16000 base_latency: 1
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outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
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switch_2_inlinks: 2
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switch_2_outlinks: 2
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links_utilized_percent_switch_2: 4.77887
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links_utilized_percent_switch_2_link_0: 6.20061 bw: 16000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 3.35713 bw: 16000 base_latency: 1
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outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
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Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory
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system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 270
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system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270
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system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
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system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
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system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
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system.ruby.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
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system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 270 100%
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Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory
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system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 240
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system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 240
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system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
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system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
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system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
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system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 75.8333%
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system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 24.1667%
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system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 240 100%
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Cache Stats: system.ruby.l1_cntrl0.L2cacheMemory
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system.ruby.l1_cntrl0.L2cacheMemory_total_misses: 510
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system.ruby.l1_cntrl0.L2cacheMemory_total_demand_misses: 510
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system.ruby.l1_cntrl0.L2cacheMemory_total_prefetches: 0
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system.ruby.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
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system.ruby.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
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system.ruby.l1_cntrl0.L2cacheMemory_request_type_LD: 35.6863%
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system.ruby.l1_cntrl0.L2cacheMemory_request_type_ST: 11.3725%
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system.ruby.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 52.9412%
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system.ruby.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 510 100%
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--- L1Cache ---
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- Event Counts -
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Load [422 ] 422
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Ifetch [2591 ] 2591
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Store [298 ] 298
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L2_Replacement [425 ] 425
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L1_to_L2 [502 ] 502
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Trigger_L2_to_L1D [47 ] 47
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Trigger_L2_to_L1I [22 ] 22
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Complete_L2_to_L1 [69 ] 69
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Other_GETX [0 ] 0
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Other_GETS [0 ] 0
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Merged_GETS [0 ] 0
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Other_GETS_No_Mig [0 ] 0
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NC_DMA_GETS [0 ] 0
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Invalidate [0 ] 0
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Ack [0 ] 0
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Shared_Ack [0 ] 0
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Data [0 ] 0
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Shared_Data [0 ] 0
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Exclusive_Data [441 ] 441
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Writeback_Ack [425 ] 425
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Writeback_Nack [0 ] 0
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All_acks [0 ] 0
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All_acks_no_sharers [441 ] 441
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Flush_line [0 ] 0
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Block_Ack [0 ] 0
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- Transitions -
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I Load [146 ] 146
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I Ifetch [248 ] 248
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I Store [47 ] 47
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I L2_Replacement [0 ] 0
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I L1_to_L2 [0 ] 0
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I Trigger_L2_to_L1D [0 ] 0
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I Trigger_L2_to_L1I [0 ] 0
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I Other_GETX [0 ] 0
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I Other_GETS [0 ] 0
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I Other_GETS_No_Mig [0 ] 0
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I NC_DMA_GETS [0 ] 0
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I Invalidate [0 ] 0
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I Flush_line [0 ] 0
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S Load [0 ] 0
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S Ifetch [0 ] 0
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S Store [0 ] 0
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S L2_Replacement [0 ] 0
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S L1_to_L2 [0 ] 0
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S Trigger_L2_to_L1D [0 ] 0
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S Trigger_L2_to_L1I [0 ] 0
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S Other_GETX [0 ] 0
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S Other_GETS [0 ] 0
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|
S Other_GETS_No_Mig [0 ] 0
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S NC_DMA_GETS [0 ] 0
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S Invalidate [0 ] 0
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S Flush_line [0 ] 0
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O Load [0 ] 0
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O Ifetch [0 ] 0
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O Store [0 ] 0
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O L2_Replacement [0 ] 0
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O L1_to_L2 [0 ] 0
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O Trigger_L2_to_L1D [0 ] 0
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O Trigger_L2_to_L1I [0 ] 0
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O Other_GETX [0 ] 0
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O Other_GETS [0 ] 0
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O Merged_GETS [0 ] 0
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O Other_GETS_No_Mig [0 ] 0
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O NC_DMA_GETS [0 ] 0
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O Invalidate [0 ] 0
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O Flush_line [0 ] 0
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M Load [109 ] 109
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M Ifetch [2315 ] 2315
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M Store [35 ] 35
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M L2_Replacement [344 ] 344
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M L1_to_L2 [397 ] 397
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M Trigger_L2_to_L1D [23 ] 23
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M Trigger_L2_to_L1I [22 ] 22
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M Other_GETX [0 ] 0
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M Other_GETS [0 ] 0
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M Merged_GETS [0 ] 0
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M Other_GETS_No_Mig [0 ] 0
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M NC_DMA_GETS [0 ] 0
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M Invalidate [0 ] 0
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M Flush_line [0 ] 0
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MM Load [124 ] 124
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MM Ifetch [0 ] 0
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MM Store [201 ] 201
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MM L2_Replacement [81 ] 81
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MM L1_to_L2 [105 ] 105
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MM Trigger_L2_to_L1D [24 ] 24
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MM Trigger_L2_to_L1I [0 ] 0
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MM Other_GETX [0 ] 0
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MM Other_GETS [0 ] 0
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MM Merged_GETS [0 ] 0
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MM Other_GETS_No_Mig [0 ] 0
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MM NC_DMA_GETS [0 ] 0
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MM Invalidate [0 ] 0
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MM Flush_line [0 ] 0
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IR Load [0 ] 0
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IR Ifetch [0 ] 0
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IR Store [0 ] 0
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IR L1_to_L2 [0 ] 0
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IR Flush_line [0 ] 0
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SR Load [0 ] 0
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SR Ifetch [0 ] 0
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SR Store [0 ] 0
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SR L1_to_L2 [0 ] 0
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SR Flush_line [0 ] 0
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OR Load [0 ] 0
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OR Ifetch [0 ] 0
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OR Store [0 ] 0
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OR L1_to_L2 [0 ] 0
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OR Flush_line [0 ] 0
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MR Load [22 ] 22
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MR Ifetch [22 ] 22
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MR Store [1 ] 1
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MR L1_to_L2 [0 ] 0
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MR Flush_line [0 ] 0
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MMR Load [14 ] 14
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MMR Ifetch [0 ] 0
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MMR Store [10 ] 10
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MMR L1_to_L2 [0 ] 0
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MMR Flush_line [0 ] 0
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IM Load [0 ] 0
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IM Ifetch [0 ] 0
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IM Store [0 ] 0
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IM L2_Replacement [0 ] 0
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IM L1_to_L2 [0 ] 0
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IM Other_GETX [0 ] 0
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IM Other_GETS [0 ] 0
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IM Other_GETS_No_Mig [0 ] 0
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IM NC_DMA_GETS [0 ] 0
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IM Invalidate [0 ] 0
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IM Ack [0 ] 0
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IM Data [0 ] 0
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IM Exclusive_Data [47 ] 47
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IM Flush_line [0 ] 0
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|
|
SM Load [0 ] 0
|
|
SM Ifetch [0 ] 0
|
|
SM Store [0 ] 0
|
|
SM L2_Replacement [0 ] 0
|
|
SM L1_to_L2 [0 ] 0
|
|
SM Other_GETX [0 ] 0
|
|
SM Other_GETS [0 ] 0
|
|
SM Other_GETS_No_Mig [0 ] 0
|
|
SM NC_DMA_GETS [0 ] 0
|
|
SM Invalidate [0 ] 0
|
|
SM Ack [0 ] 0
|
|
SM Data [0 ] 0
|
|
SM Exclusive_Data [0 ] 0
|
|
SM Flush_line [0 ] 0
|
|
|
|
OM Load [0 ] 0
|
|
OM Ifetch [0 ] 0
|
|
OM Store [0 ] 0
|
|
OM L2_Replacement [0 ] 0
|
|
OM L1_to_L2 [0 ] 0
|
|
OM Other_GETX [0 ] 0
|
|
OM Other_GETS [0 ] 0
|
|
OM Merged_GETS [0 ] 0
|
|
OM Other_GETS_No_Mig [0 ] 0
|
|
OM NC_DMA_GETS [0 ] 0
|
|
OM Invalidate [0 ] 0
|
|
OM Ack [0 ] 0
|
|
OM All_acks [0 ] 0
|
|
OM All_acks_no_sharers [0 ] 0
|
|
OM Flush_line [0 ] 0
|
|
|
|
ISM Load [0 ] 0
|
|
ISM Ifetch [0 ] 0
|
|
ISM Store [0 ] 0
|
|
ISM L2_Replacement [0 ] 0
|
|
ISM L1_to_L2 [0 ] 0
|
|
ISM Ack [0 ] 0
|
|
ISM All_acks_no_sharers [0 ] 0
|
|
ISM Flush_line [0 ] 0
|
|
|
|
M_W Load [0 ] 0
|
|
M_W Ifetch [0 ] 0
|
|
M_W Store [0 ] 0
|
|
M_W L2_Replacement [0 ] 0
|
|
M_W L1_to_L2 [0 ] 0
|
|
M_W Ack [0 ] 0
|
|
M_W All_acks_no_sharers [394 ] 394
|
|
M_W Flush_line [0 ] 0
|
|
|
|
MM_W Load [0 ] 0
|
|
MM_W Ifetch [0 ] 0
|
|
MM_W Store [0 ] 0
|
|
MM_W L2_Replacement [0 ] 0
|
|
MM_W L1_to_L2 [0 ] 0
|
|
MM_W Ack [0 ] 0
|
|
MM_W All_acks_no_sharers [47 ] 47
|
|
MM_W Flush_line [0 ] 0
|
|
|
|
IS Load [0 ] 0
|
|
IS Ifetch [0 ] 0
|
|
IS Store [0 ] 0
|
|
IS L2_Replacement [0 ] 0
|
|
IS L1_to_L2 [0 ] 0
|
|
IS Other_GETX [0 ] 0
|
|
IS Other_GETS [0 ] 0
|
|
IS Other_GETS_No_Mig [0 ] 0
|
|
IS NC_DMA_GETS [0 ] 0
|
|
IS Invalidate [0 ] 0
|
|
IS Ack [0 ] 0
|
|
IS Shared_Ack [0 ] 0
|
|
IS Data [0 ] 0
|
|
IS Shared_Data [0 ] 0
|
|
IS Exclusive_Data [394 ] 394
|
|
IS Flush_line [0 ] 0
|
|
|
|
SS Load [0 ] 0
|
|
SS Ifetch [0 ] 0
|
|
SS Store [0 ] 0
|
|
SS L2_Replacement [0 ] 0
|
|
SS L1_to_L2 [0 ] 0
|
|
SS Ack [0 ] 0
|
|
SS Shared_Ack [0 ] 0
|
|
SS All_acks [0 ] 0
|
|
SS All_acks_no_sharers [0 ] 0
|
|
SS Flush_line [0 ] 0
|
|
|
|
OI Load [0 ] 0
|
|
OI Ifetch [0 ] 0
|
|
OI Store [0 ] 0
|
|
OI L2_Replacement [0 ] 0
|
|
OI L1_to_L2 [0 ] 0
|
|
OI Other_GETX [0 ] 0
|
|
OI Other_GETS [0 ] 0
|
|
OI Merged_GETS [0 ] 0
|
|
OI Other_GETS_No_Mig [0 ] 0
|
|
OI NC_DMA_GETS [0 ] 0
|
|
OI Invalidate [0 ] 0
|
|
OI Writeback_Ack [0 ] 0
|
|
OI Flush_line [0 ] 0
|
|
|
|
MI Load [7 ] 7
|
|
MI Ifetch [6 ] 6
|
|
MI Store [4 ] 4
|
|
MI L2_Replacement [0 ] 0
|
|
MI L1_to_L2 [0 ] 0
|
|
MI Other_GETX [0 ] 0
|
|
MI Other_GETS [0 ] 0
|
|
MI Merged_GETS [0 ] 0
|
|
MI Other_GETS_No_Mig [0 ] 0
|
|
MI NC_DMA_GETS [0 ] 0
|
|
MI Invalidate [0 ] 0
|
|
MI Writeback_Ack [425 ] 425
|
|
MI Flush_line [0 ] 0
|
|
|
|
II Load [0 ] 0
|
|
II Ifetch [0 ] 0
|
|
II Store [0 ] 0
|
|
II L2_Replacement [0 ] 0
|
|
II L1_to_L2 [0 ] 0
|
|
II Other_GETX [0 ] 0
|
|
II Other_GETS [0 ] 0
|
|
II Other_GETS_No_Mig [0 ] 0
|
|
II NC_DMA_GETS [0 ] 0
|
|
II Invalidate [0 ] 0
|
|
II Writeback_Ack [0 ] 0
|
|
II Writeback_Nack [0 ] 0
|
|
II Flush_line [0 ] 0
|
|
|
|
IT Load [0 ] 0
|
|
IT Ifetch [0 ] 0
|
|
IT Store [0 ] 0
|
|
IT L2_Replacement [0 ] 0
|
|
IT L1_to_L2 [0 ] 0
|
|
IT Complete_L2_to_L1 [0 ] 0
|
|
|
|
ST Load [0 ] 0
|
|
ST Ifetch [0 ] 0
|
|
ST Store [0 ] 0
|
|
ST L2_Replacement [0 ] 0
|
|
ST L1_to_L2 [0 ] 0
|
|
ST Complete_L2_to_L1 [0 ] 0
|
|
|
|
OT Load [0 ] 0
|
|
OT Ifetch [0 ] 0
|
|
OT Store [0 ] 0
|
|
OT L2_Replacement [0 ] 0
|
|
OT L1_to_L2 [0 ] 0
|
|
OT Complete_L2_to_L1 [0 ] 0
|
|
|
|
MT Load [0 ] 0
|
|
MT Ifetch [0 ] 0
|
|
MT Store [0 ] 0
|
|
MT L2_Replacement [0 ] 0
|
|
MT L1_to_L2 [0 ] 0
|
|
MT Complete_L2_to_L1 [45 ] 45
|
|
|
|
MMT Load [0 ] 0
|
|
MMT Ifetch [0 ] 0
|
|
MMT Store [0 ] 0
|
|
MMT L2_Replacement [0 ] 0
|
|
MMT L1_to_L2 [0 ] 0
|
|
MMT Complete_L2_to_L1 [24 ] 24
|
|
|
|
MI_F Load [0 ] 0
|
|
MI_F Ifetch [0 ] 0
|
|
MI_F Store [0 ] 0
|
|
MI_F L1_to_L2 [0 ] 0
|
|
MI_F Writeback_Ack [0 ] 0
|
|
MI_F Flush_line [0 ] 0
|
|
|
|
MM_F Load [0 ] 0
|
|
MM_F Ifetch [0 ] 0
|
|
MM_F Store [0 ] 0
|
|
MM_F L1_to_L2 [0 ] 0
|
|
MM_F Other_GETX [0 ] 0
|
|
MM_F Other_GETS [0 ] 0
|
|
MM_F Merged_GETS [0 ] 0
|
|
MM_F Other_GETS_No_Mig [0 ] 0
|
|
MM_F NC_DMA_GETS [0 ] 0
|
|
MM_F Invalidate [0 ] 0
|
|
MM_F Ack [0 ] 0
|
|
MM_F All_acks [0 ] 0
|
|
MM_F All_acks_no_sharers [0 ] 0
|
|
MM_F Flush_line [0 ] 0
|
|
MM_F Block_Ack [0 ] 0
|
|
|
|
IM_F Load [0 ] 0
|
|
IM_F Ifetch [0 ] 0
|
|
IM_F Store [0 ] 0
|
|
IM_F L2_Replacement [0 ] 0
|
|
IM_F L1_to_L2 [0 ] 0
|
|
IM_F Other_GETX [0 ] 0
|
|
IM_F Other_GETS [0 ] 0
|
|
IM_F Other_GETS_No_Mig [0 ] 0
|
|
IM_F NC_DMA_GETS [0 ] 0
|
|
IM_F Invalidate [0 ] 0
|
|
IM_F Ack [0 ] 0
|
|
IM_F Data [0 ] 0
|
|
IM_F Exclusive_Data [0 ] 0
|
|
IM_F Flush_line [0 ] 0
|
|
|
|
ISM_F Load [0 ] 0
|
|
ISM_F Ifetch [0 ] 0
|
|
ISM_F Store [0 ] 0
|
|
ISM_F L2_Replacement [0 ] 0
|
|
ISM_F L1_to_L2 [0 ] 0
|
|
ISM_F Ack [0 ] 0
|
|
ISM_F All_acks_no_sharers [0 ] 0
|
|
ISM_F Flush_line [0 ] 0
|
|
|
|
SM_F Load [0 ] 0
|
|
SM_F Ifetch [0 ] 0
|
|
SM_F Store [0 ] 0
|
|
SM_F L2_Replacement [0 ] 0
|
|
SM_F L1_to_L2 [0 ] 0
|
|
SM_F Other_GETX [0 ] 0
|
|
SM_F Other_GETS [0 ] 0
|
|
SM_F Other_GETS_No_Mig [0 ] 0
|
|
SM_F NC_DMA_GETS [0 ] 0
|
|
SM_F Invalidate [0 ] 0
|
|
SM_F Ack [0 ] 0
|
|
SM_F Data [0 ] 0
|
|
SM_F Exclusive_Data [0 ] 0
|
|
SM_F Flush_line [0 ] 0
|
|
|
|
OM_F Load [0 ] 0
|
|
OM_F Ifetch [0 ] 0
|
|
OM_F Store [0 ] 0
|
|
OM_F L2_Replacement [0 ] 0
|
|
OM_F L1_to_L2 [0 ] 0
|
|
OM_F Other_GETX [0 ] 0
|
|
OM_F Other_GETS [0 ] 0
|
|
OM_F Merged_GETS [0 ] 0
|
|
OM_F Other_GETS_No_Mig [0 ] 0
|
|
OM_F NC_DMA_GETS [0 ] 0
|
|
OM_F Invalidate [0 ] 0
|
|
OM_F Ack [0 ] 0
|
|
OM_F All_acks [0 ] 0
|
|
OM_F All_acks_no_sharers [0 ] 0
|
|
OM_F Flush_line [0 ] 0
|
|
|
|
MM_WF Load [0 ] 0
|
|
MM_WF Ifetch [0 ] 0
|
|
MM_WF Store [0 ] 0
|
|
MM_WF L2_Replacement [0 ] 0
|
|
MM_WF L1_to_L2 [0 ] 0
|
|
MM_WF Ack [0 ] 0
|
|
MM_WF All_acks_no_sharers [0 ] 0
|
|
MM_WF Flush_line [0 ] 0
|
|
|
|
Cache Stats: system.ruby.dir_cntrl0.probeFilter
|
|
system.ruby.dir_cntrl0.probeFilter_total_misses: 0
|
|
system.ruby.dir_cntrl0.probeFilter_total_demand_misses: 0
|
|
system.ruby.dir_cntrl0.probeFilter_total_prefetches: 0
|
|
system.ruby.dir_cntrl0.probeFilter_total_sw_prefetches: 0
|
|
system.ruby.dir_cntrl0.probeFilter_total_hw_prefetches: 0
|
|
|
|
|
|
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
|
memory_total_requests: 522
|
|
memory_reads: 441
|
|
memory_writes: 81
|
|
memory_refreshes: 246
|
|
memory_total_request_delays: 39
|
|
memory_delays_per_request: 0.0747126
|
|
memory_delays_in_input_queue: 0
|
|
memory_delays_behind_head_of_bank_queue: 0
|
|
memory_delays_stalled_at_head_of_bank_queue: 39
|
|
memory_stalls_for_bank_busy: 15
|
|
memory_stalls_for_random_busy: 0
|
|
memory_stalls_for_anti_starvation: 0
|
|
memory_stalls_for_arbitration: 5
|
|
memory_stalls_for_bus: 15
|
|
memory_stalls_for_tfaw: 0
|
|
memory_stalls_for_read_write_turnaround: 4
|
|
memory_stalls_for_read_read_turnaround: 0
|
|
accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
|
|
|
|
--- Directory ---
|
|
- Event Counts -
|
|
GETX [51 ] 51
|
|
GETS [410 ] 410
|
|
PUT [425 ] 425
|
|
Unblock [0 ] 0
|
|
UnblockS [0 ] 0
|
|
UnblockM [440 ] 440
|
|
Writeback_Clean [0 ] 0
|
|
Writeback_Dirty [0 ] 0
|
|
Writeback_Exclusive_Clean [344 ] 344
|
|
Writeback_Exclusive_Dirty [81 ] 81
|
|
Pf_Replacement [0 ] 0
|
|
DMA_READ [0 ] 0
|
|
DMA_WRITE [0 ] 0
|
|
Memory_Data [441 ] 441
|
|
Memory_Ack [81 ] 81
|
|
Ack [0 ] 0
|
|
Shared_Ack [0 ] 0
|
|
Shared_Data [0 ] 0
|
|
Data [0 ] 0
|
|
Exclusive_Data [0 ] 0
|
|
All_acks_and_shared_data [0 ] 0
|
|
All_acks_and_owner_data [0 ] 0
|
|
All_acks_and_data_no_sharers [0 ] 0
|
|
All_Unblocks [0 ] 0
|
|
GETF [0 ] 0
|
|
PUTF [0 ] 0
|
|
|
|
- Transitions -
|
|
NX GETX [0 ] 0
|
|
NX GETS [0 ] 0
|
|
NX PUT [0 ] 0
|
|
NX Pf_Replacement [0 ] 0
|
|
NX DMA_READ [0 ] 0
|
|
NX DMA_WRITE [0 ] 0
|
|
NX GETF [0 ] 0
|
|
|
|
NO GETX [0 ] 0
|
|
NO GETS [0 ] 0
|
|
NO PUT [425 ] 425
|
|
NO Pf_Replacement [0 ] 0
|
|
NO DMA_READ [0 ] 0
|
|
NO DMA_WRITE [0 ] 0
|
|
NO GETF [0 ] 0
|
|
|
|
S GETX [0 ] 0
|
|
S GETS [0 ] 0
|
|
S PUT [0 ] 0
|
|
S Pf_Replacement [0 ] 0
|
|
S DMA_READ [0 ] 0
|
|
S DMA_WRITE [0 ] 0
|
|
S GETF [0 ] 0
|
|
|
|
O GETX [0 ] 0
|
|
O GETS [0 ] 0
|
|
O PUT [0 ] 0
|
|
O Pf_Replacement [0 ] 0
|
|
O DMA_READ [0 ] 0
|
|
O DMA_WRITE [0 ] 0
|
|
O GETF [0 ] 0
|
|
|
|
E GETX [47 ] 47
|
|
E GETS [394 ] 394
|
|
E PUT [0 ] 0
|
|
E DMA_READ [0 ] 0
|
|
E DMA_WRITE [0 ] 0
|
|
E GETF [0 ] 0
|
|
|
|
O_R GETX [0 ] 0
|
|
O_R GETS [0 ] 0
|
|
O_R PUT [0 ] 0
|
|
O_R Pf_Replacement [0 ] 0
|
|
O_R DMA_READ [0 ] 0
|
|
O_R DMA_WRITE [0 ] 0
|
|
O_R Ack [0 ] 0
|
|
O_R All_acks_and_data_no_sharers [0 ] 0
|
|
O_R GETF [0 ] 0
|
|
|
|
S_R GETX [0 ] 0
|
|
S_R GETS [0 ] 0
|
|
S_R PUT [0 ] 0
|
|
S_R Pf_Replacement [0 ] 0
|
|
S_R DMA_READ [0 ] 0
|
|
S_R DMA_WRITE [0 ] 0
|
|
S_R Ack [0 ] 0
|
|
S_R Data [0 ] 0
|
|
S_R All_acks_and_data_no_sharers [0 ] 0
|
|
S_R GETF [0 ] 0
|
|
|
|
NO_R GETX [0 ] 0
|
|
NO_R GETS [0 ] 0
|
|
NO_R PUT [0 ] 0
|
|
NO_R Pf_Replacement [0 ] 0
|
|
NO_R DMA_READ [0 ] 0
|
|
NO_R DMA_WRITE [0 ] 0
|
|
NO_R Ack [0 ] 0
|
|
NO_R Data [0 ] 0
|
|
NO_R Exclusive_Data [0 ] 0
|
|
NO_R All_acks_and_data_no_sharers [0 ] 0
|
|
NO_R GETF [0 ] 0
|
|
|
|
NO_B GETX [0 ] 0
|
|
NO_B GETS [0 ] 0
|
|
NO_B PUT [0 ] 0
|
|
NO_B UnblockS [0 ] 0
|
|
NO_B UnblockM [440 ] 440
|
|
NO_B Pf_Replacement [0 ] 0
|
|
NO_B DMA_READ [0 ] 0
|
|
NO_B DMA_WRITE [0 ] 0
|
|
NO_B GETF [0 ] 0
|
|
|
|
NO_B_X GETX [0 ] 0
|
|
NO_B_X GETS [0 ] 0
|
|
NO_B_X PUT [0 ] 0
|
|
NO_B_X UnblockS [0 ] 0
|
|
NO_B_X UnblockM [0 ] 0
|
|
NO_B_X Pf_Replacement [0 ] 0
|
|
NO_B_X DMA_READ [0 ] 0
|
|
NO_B_X DMA_WRITE [0 ] 0
|
|
NO_B_X GETF [0 ] 0
|
|
|
|
NO_B_S GETX [0 ] 0
|
|
NO_B_S GETS [0 ] 0
|
|
NO_B_S PUT [0 ] 0
|
|
NO_B_S UnblockS [0 ] 0
|
|
NO_B_S UnblockM [0 ] 0
|
|
NO_B_S Pf_Replacement [0 ] 0
|
|
NO_B_S DMA_READ [0 ] 0
|
|
NO_B_S DMA_WRITE [0 ] 0
|
|
NO_B_S GETF [0 ] 0
|
|
|
|
NO_B_S_W GETX [0 ] 0
|
|
NO_B_S_W GETS [0 ] 0
|
|
NO_B_S_W PUT [0 ] 0
|
|
NO_B_S_W UnblockS [0 ] 0
|
|
NO_B_S_W Pf_Replacement [0 ] 0
|
|
NO_B_S_W DMA_READ [0 ] 0
|
|
NO_B_S_W DMA_WRITE [0 ] 0
|
|
NO_B_S_W All_Unblocks [0 ] 0
|
|
NO_B_S_W GETF [0 ] 0
|
|
|
|
O_B GETX [0 ] 0
|
|
O_B GETS [0 ] 0
|
|
O_B PUT [0 ] 0
|
|
O_B UnblockS [0 ] 0
|
|
O_B UnblockM [0 ] 0
|
|
O_B Pf_Replacement [0 ] 0
|
|
O_B DMA_READ [0 ] 0
|
|
O_B DMA_WRITE [0 ] 0
|
|
O_B GETF [0 ] 0
|
|
|
|
NO_B_W GETX [0 ] 0
|
|
NO_B_W GETS [0 ] 0
|
|
NO_B_W PUT [0 ] 0
|
|
NO_B_W UnblockS [0 ] 0
|
|
NO_B_W UnblockM [0 ] 0
|
|
NO_B_W Pf_Replacement [0 ] 0
|
|
NO_B_W DMA_READ [0 ] 0
|
|
NO_B_W DMA_WRITE [0 ] 0
|
|
NO_B_W Memory_Data [441 ] 441
|
|
NO_B_W GETF [0 ] 0
|
|
|
|
O_B_W GETX [0 ] 0
|
|
O_B_W GETS [0 ] 0
|
|
O_B_W PUT [0 ] 0
|
|
O_B_W UnblockS [0 ] 0
|
|
O_B_W Pf_Replacement [0 ] 0
|
|
O_B_W DMA_READ [0 ] 0
|
|
O_B_W DMA_WRITE [0 ] 0
|
|
O_B_W Memory_Data [0 ] 0
|
|
O_B_W GETF [0 ] 0
|
|
|
|
NO_W GETX [0 ] 0
|
|
NO_W GETS [0 ] 0
|
|
NO_W PUT [0 ] 0
|
|
NO_W Pf_Replacement [0 ] 0
|
|
NO_W DMA_READ [0 ] 0
|
|
NO_W DMA_WRITE [0 ] 0
|
|
NO_W Memory_Data [0 ] 0
|
|
NO_W GETF [0 ] 0
|
|
|
|
O_W GETX [0 ] 0
|
|
O_W GETS [0 ] 0
|
|
O_W PUT [0 ] 0
|
|
O_W Pf_Replacement [0 ] 0
|
|
O_W DMA_READ [0 ] 0
|
|
O_W DMA_WRITE [0 ] 0
|
|
O_W Memory_Data [0 ] 0
|
|
O_W GETF [0 ] 0
|
|
|
|
NO_DW_B_W GETX [0 ] 0
|
|
NO_DW_B_W GETS [0 ] 0
|
|
NO_DW_B_W PUT [0 ] 0
|
|
NO_DW_B_W Pf_Replacement [0 ] 0
|
|
NO_DW_B_W DMA_READ [0 ] 0
|
|
NO_DW_B_W DMA_WRITE [0 ] 0
|
|
NO_DW_B_W Ack [0 ] 0
|
|
NO_DW_B_W Data [0 ] 0
|
|
NO_DW_B_W Exclusive_Data [0 ] 0
|
|
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
|
|
NO_DW_B_W GETF [0 ] 0
|
|
|
|
NO_DR_B_W GETX [0 ] 0
|
|
NO_DR_B_W GETS [0 ] 0
|
|
NO_DR_B_W PUT [0 ] 0
|
|
NO_DR_B_W Pf_Replacement [0 ] 0
|
|
NO_DR_B_W DMA_READ [0 ] 0
|
|
NO_DR_B_W DMA_WRITE [0 ] 0
|
|
NO_DR_B_W Memory_Data [0 ] 0
|
|
NO_DR_B_W Ack [0 ] 0
|
|
NO_DR_B_W Shared_Ack [0 ] 0
|
|
NO_DR_B_W Shared_Data [0 ] 0
|
|
NO_DR_B_W Data [0 ] 0
|
|
NO_DR_B_W Exclusive_Data [0 ] 0
|
|
NO_DR_B_W GETF [0 ] 0
|
|
|
|
NO_DR_B_D GETX [0 ] 0
|
|
NO_DR_B_D GETS [0 ] 0
|
|
NO_DR_B_D PUT [0 ] 0
|
|
NO_DR_B_D Pf_Replacement [0 ] 0
|
|
NO_DR_B_D DMA_READ [0 ] 0
|
|
NO_DR_B_D DMA_WRITE [0 ] 0
|
|
NO_DR_B_D Ack [0 ] 0
|
|
NO_DR_B_D Shared_Ack [0 ] 0
|
|
NO_DR_B_D Shared_Data [0 ] 0
|
|
NO_DR_B_D Data [0 ] 0
|
|
NO_DR_B_D Exclusive_Data [0 ] 0
|
|
NO_DR_B_D All_acks_and_shared_data [0 ] 0
|
|
NO_DR_B_D All_acks_and_owner_data [0 ] 0
|
|
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
|
|
NO_DR_B_D GETF [0 ] 0
|
|
|
|
NO_DR_B GETX [0 ] 0
|
|
NO_DR_B GETS [0 ] 0
|
|
NO_DR_B PUT [0 ] 0
|
|
NO_DR_B Pf_Replacement [0 ] 0
|
|
NO_DR_B DMA_READ [0 ] 0
|
|
NO_DR_B DMA_WRITE [0 ] 0
|
|
NO_DR_B Ack [0 ] 0
|
|
NO_DR_B Shared_Ack [0 ] 0
|
|
NO_DR_B Shared_Data [0 ] 0
|
|
NO_DR_B Data [0 ] 0
|
|
NO_DR_B Exclusive_Data [0 ] 0
|
|
NO_DR_B All_acks_and_shared_data [0 ] 0
|
|
NO_DR_B All_acks_and_owner_data [0 ] 0
|
|
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
|
|
NO_DR_B GETF [0 ] 0
|
|
|
|
NO_DW_W GETX [0 ] 0
|
|
NO_DW_W GETS [0 ] 0
|
|
NO_DW_W PUT [0 ] 0
|
|
NO_DW_W Pf_Replacement [0 ] 0
|
|
NO_DW_W DMA_READ [0 ] 0
|
|
NO_DW_W DMA_WRITE [0 ] 0
|
|
NO_DW_W Memory_Ack [0 ] 0
|
|
NO_DW_W GETF [0 ] 0
|
|
|
|
O_DR_B_W GETX [0 ] 0
|
|
O_DR_B_W GETS [0 ] 0
|
|
O_DR_B_W PUT [0 ] 0
|
|
O_DR_B_W Pf_Replacement [0 ] 0
|
|
O_DR_B_W DMA_READ [0 ] 0
|
|
O_DR_B_W DMA_WRITE [0 ] 0
|
|
O_DR_B_W Memory_Data [0 ] 0
|
|
O_DR_B_W Ack [0 ] 0
|
|
O_DR_B_W Shared_Ack [0 ] 0
|
|
O_DR_B_W GETF [0 ] 0
|
|
|
|
O_DR_B GETX [0 ] 0
|
|
O_DR_B GETS [0 ] 0
|
|
O_DR_B PUT [0 ] 0
|
|
O_DR_B Pf_Replacement [0 ] 0
|
|
O_DR_B DMA_READ [0 ] 0
|
|
O_DR_B DMA_WRITE [0 ] 0
|
|
O_DR_B Ack [0 ] 0
|
|
O_DR_B Shared_Ack [0 ] 0
|
|
O_DR_B All_acks_and_owner_data [0 ] 0
|
|
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
|
O_DR_B GETF [0 ] 0
|
|
|
|
WB GETX [4 ] 4
|
|
WB GETS [14 ] 14
|
|
WB PUT [0 ] 0
|
|
WB Unblock [0 ] 0
|
|
WB Writeback_Clean [0 ] 0
|
|
WB Writeback_Dirty [0 ] 0
|
|
WB Writeback_Exclusive_Clean [344 ] 344
|
|
WB Writeback_Exclusive_Dirty [81 ] 81
|
|
WB Pf_Replacement [0 ] 0
|
|
WB DMA_READ [0 ] 0
|
|
WB DMA_WRITE [0 ] 0
|
|
WB GETF [0 ] 0
|
|
|
|
WB_O_W GETX [0 ] 0
|
|
WB_O_W GETS [0 ] 0
|
|
WB_O_W PUT [0 ] 0
|
|
WB_O_W Pf_Replacement [0 ] 0
|
|
WB_O_W DMA_READ [0 ] 0
|
|
WB_O_W DMA_WRITE [0 ] 0
|
|
WB_O_W Memory_Ack [0 ] 0
|
|
WB_O_W GETF [0 ] 0
|
|
|
|
WB_E_W GETX [0 ] 0
|
|
WB_E_W GETS [2 ] 2
|
|
WB_E_W PUT [0 ] 0
|
|
WB_E_W Pf_Replacement [0 ] 0
|
|
WB_E_W DMA_READ [0 ] 0
|
|
WB_E_W DMA_WRITE [0 ] 0
|
|
WB_E_W Memory_Ack [81 ] 81
|
|
WB_E_W GETF [0 ] 0
|
|
|
|
NO_F GETX [0 ] 0
|
|
NO_F GETS [0 ] 0
|
|
NO_F PUT [0 ] 0
|
|
NO_F UnblockM [0 ] 0
|
|
NO_F Pf_Replacement [0 ] 0
|
|
NO_F GETF [0 ] 0
|
|
NO_F PUTF [0 ] 0
|
|
|
|
NO_F_W GETX [0 ] 0
|
|
NO_F_W GETS [0 ] 0
|
|
NO_F_W PUT [0 ] 0
|
|
NO_F_W Pf_Replacement [0 ] 0
|
|
NO_F_W DMA_READ [0 ] 0
|
|
NO_F_W DMA_WRITE [0 ] 0
|
|
NO_F_W Memory_Data [0 ] 0
|
|
NO_F_W GETF [0 ] 0
|
|
|