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gem5/src/sim
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Joel Hestness 395b31f518 syscall_emul: Bandage readlink /proc/self/exe 
The recent changeset to readlink() to handle reading the /proc/self/exe link
introduces a number of problems. This patch fixes two:

1) Because readlink() called on /proc/self/exe now uses LiveProcess::progName()
to find the binary path, it will only get the zeroth parameter of the simulated
system command line. However, if a config script also specifies the process'
executable, the executable parameter is used to create the LiveProcess rather
than the zeroth command line parameter. Thus, the zeroth command line parameter
is not necessarily the correct path to the binary executing in the simulated
system. To fix this, add a LiveProcess data member, 'executable', which is
correctly set during instantiation and returned from progName().

2) If a config script allows a user to pass a relative path as the zeroth
simulated system command line parameter or process executable, readlink() will
incorrecly return a relative path when called on '/proc/self/exe'.
/proc/self/exe is always set to a full path, so running benchmarks can fail if
a relative path is returned. To fix this, clean up the handling of
LiveProcess::progName() within readlink() to get the full binary path.

NOTE: This patch still leaves the potential problem that host full path to the
binary bleeds into the simulated system, potentially causing the appearance of
non-deterministic simulated system execution.
2015-09-29 09:25:20 -05:00
..
probe mem: Add PacketInfo to be used for packet probe points 2015-09-25 13:25:34 -04:00
arguments.cc GetArgument: Rework getArgument so that X86_FS compiles again. 2010-10-15 23:57:06 -07:00
arguments.hh dev: Use shared_ptr for Arguments::Data 2014-10-16 05:49:45 -04:00
async.cc base: Fix race in PollQueue and remove SIGALRM workaround 2013-11-29 14:36:10 +01:00
async.hh base: Fix race in PollQueue and remove SIGALRM workaround 2013-11-29 14:36:10 +01:00
byteswap.hh base: Redesign internal frame buffer handling 2015-05-23 13:37:03 +01:00
clock_domain.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
clock_domain.hh sim: Split ClockedObject to make it usable to non-SimObjects 2015-08-07 09:59:22 +01:00
ClockDomain.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
clocked_object.hh sim: clocked object: function for converting cycles to ticks. 2015-08-11 11:39:23 -05:00
ClockedObject.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
core.cc sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
core.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
cxx_config.cc config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_config.hh config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_config_ini.cc config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_config_ini.hh config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_manager.cc sim: Decouple draining from the SimObject hierarchy 2015-07-07 09:51:05 +01:00
cxx_manager.hh sim: Decouple draining from the SimObject hierarchy 2015-07-07 09:51:05 +01:00
debug.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
debug.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
drain.cc sim: Initialize Drainable::_drainState to the system's state 2015-08-04 10:31:37 +01:00
drain.hh sim: Fixup comments and constness in draining infrastructure 2015-08-05 10:27:11 +01:00
dvfs_handler.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
dvfs_handler.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
DVFSHandler.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
emul_driver.hh syscall_emul: add EmulatedDriver object 2014-10-22 15:53:34 -07:00
eventq.cc sim: Remove broken AutoSerialize support from the event queue 2015-09-01 15:28:45 +01:00
eventq.hh sim: Remove broken AutoSerialize support from the event queue 2015-09-01 15:28:45 +01:00
eventq_impl.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
faults.cc cpu: Remove all notion that we know when the cpu is misspeculating. 2015-01-25 07:22:26 -05:00
faults.hh arch: Use shared_ptr for all Faults 2014-10-16 05:49:51 -04:00
fd_entry.cc base: refactor process class (specifically FdMap and friends) 2015-07-24 12:25:22 -07:00
fd_entry.hh base: refactor process class (specifically FdMap and friends) 2015-07-24 12:25:22 -07:00
full_system.hh clang: Fix recently introduced clang compilation errors 2012-03-19 06:35:04 -04:00
global_event.cc sim: Fix resource leak in BaseGlobalEvent 2014-09-09 04:36:32 -04:00
global_event.hh sim: Fix resource leak in BaseGlobalEvent 2014-09-09 04:36:32 -04:00
init.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
init.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
init_signals.cc sim: Fix time unit in abort message 2015-09-04 13:13:55 -04:00
init_signals.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
insttracer.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
InstTracer.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
main.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
microcode_rom.hh CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
process.cc syscall_emul: Bandage readlink /proc/self/exe 2015-09-29 09:25:20 -05:00
process.hh syscall_emul: Bandage readlink /proc/self/exe 2015-09-29 09:25:20 -05:00
Process.py mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
process_impl.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
pseudo_inst.cc cpu: quiesce pseudoinsts: Always do full quiesce 2015-08-26 14:20:30 -05:00
pseudo_inst.hh sim: Add a helper function to execute pseudo instructions 2013-04-22 13:20:32 -04:00
py_interact.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
py_interact.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
root.cc sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
root.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
Root.py sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
SConscript sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
serialize.cc sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
serialize.hh sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
sim_events.cc sim: Remove autoserialize support for exit events 2015-09-01 13:41:45 +01:00
sim_events.hh sim: Remove autoserialize support for exit events 2015-09-01 13:41:45 +01:00
sim_exit.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
sim_object.cc sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
sim_object.hh sim: Move SimObject resolver to sim_object.hh 2015-09-01 13:40:05 +01:00
simulate.cc sim: Update limit_event reuse to final version 2015-03-26 11:16:44 -04:00
simulate.hh sim: Update limit_event reuse to final version 2015-03-26 11:16:44 -04:00
stat_control.cc style: Fix line continuation, especially in debug messages 2014-09-12 10:22:47 -04:00
stat_control.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
stat_register.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
stat_register.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
stats.hh stats: make simTicks and simFreq accessible from stats.hh 2010-04-18 13:23:25 -07:00
sub_system.cc config: Add SubSystem container for simobjects 2014-08-10 05:39:16 -04:00
sub_system.hh config: Add SubSystem container for simobjects 2014-08-10 05:39:16 -04:00
SubSystem.py config: Add SubSystem container for simobjects 2014-08-10 05:39:16 -04:00
syscall_emul.cc syscall_emul: Bandage readlink /proc/self/exe 2015-09-29 09:25:20 -05:00
syscall_emul.hh style: change Process function calls to use camelCase 2015-07-24 12:25:23 -07:00
syscall_emul_buf.hh syscall_emul: devirtualize BaseBufferArg methods 2014-10-22 15:53:34 -07:00
syscallreturn.hh syscall_emul: add retry flag to SyscallReturn 2014-09-02 16:07:50 -05:00
system.cc base: Declare a type for context IDs 2015-08-07 09:59:13 +01:00
system.hh base: Declare a type for context IDs 2015-08-07 09:59:13 +01:00
System.py mem: mmap the backing store with MAP_NORESERVE 2015-02-16 03:33:47 -05:00
ticked_object.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
ticked_object.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
TickedObject.py cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
voltage_domain.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
voltage_domain.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
VoltageDomain.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
vptr.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00