gem5/arch/sparc/utility.hh
Gabe Black 818f3ae22f SPARC compiles for SE!
arch/sparc/isa/decoder.isa:
    Replaced register number munging with RdLow and RdHigh operands.
arch/sparc/isa/formats/mem.isa:
    Fixed how the address calculation code is dealt with.
arch/sparc/isa/operands.isa:
    Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one.
arch/sparc/isa_traits.hh:
    Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate.
arch/sparc/regfile.hh:
    Changed regSpace to have the correct size.
arch/sparc/utility.hh:
    A new file for sparc to match the one for alpha.

--HG--
extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932
2006-03-28 19:36:34 -05:00

89 lines
3 KiB
C++

/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_SPARC_UTILITY_HH__
#define __ARCH_SPARC_UTILITY_HH__
#include "arch/sparc/isa_traits.hh"
#include "base/misc.hh"
namespace SparcISA
{
inline ExtMachInst
makeExtMI(MachInst inst, const Addr &pc) {
return ExtMachInst(inst);
}
inline bool isCallerSaveIntegerRegister(unsigned int reg) {
panic("register classification not implemented");
return false;
}
inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
panic("register classification not implemented");
return false;
}
inline bool isCallerSaveFloatRegister(unsigned int reg) {
panic("register classification not implemented");
return false;
}
inline bool isCalleeSaveFloatRegister(unsigned int reg) {
panic("register classification not implemented");
return false;
}
// Instruction address compression hooks
inline Addr realPCToFetchPC(const Addr &addr)
{
return addr;
}
inline Addr fetchPCToRealPC(const Addr &addr)
{
return addr;
}
// the size of "fetched" instructions (not necessarily the size
// of real instructions for PISA)
inline size_t fetchInstSize()
{
return sizeof(MachInst);
}
/**
* Function to insure ISA semantics about 0 registers.
* @param xc The execution context.
*/
template <class XC>
void zeroRegisters(XC *xc);
} // namespace SparcISA
#endif