e99c56f971
Each "strand" may need to have a private copy of this state, but I couldn't find anywhere in the spec that said that after looking briefly. This prevents writes to the thread context in o3 which was causing the pipeline to be flushed and stopping any forward progress. The other ASI accessible state will probably need to be accessed differently if/when we get O3 full system up and running. --HG-- extra : convert_revision : fa7fba812d7f76564ef4a23818e60f536710d557
386 lines
13 KiB
C++
386 lines
13 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#include "arch/sparc/regfile.hh"
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#include "cpu/thread_context.hh"
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class Checkpoint;
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using namespace SparcISA;
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using namespace std;
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//RegFile class methods
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Addr RegFile::readPC()
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{
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return pc;
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}
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void RegFile::setPC(Addr val)
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{
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pc = val;
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}
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Addr RegFile::readNextPC()
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{
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return npc;
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}
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void RegFile::setNextPC(Addr val)
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{
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npc = val;
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}
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Addr RegFile::readNextNPC()
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{
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return nnpc;
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}
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void RegFile::setNextNPC(Addr val)
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{
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nnpc = val;
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}
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void RegFile::clear()
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{
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floatRegFile.clear();
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intRegFile.clear();
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miscRegFile.clear();
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}
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MiscReg RegFile::readMiscRegNoEffect(int miscReg)
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{
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return miscRegFile.readRegNoEffect(miscReg);
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}
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MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
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{
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return miscRegFile.readReg(miscReg, tc);
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}
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void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
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{
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miscRegFile.setRegNoEffect(miscReg, val);
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}
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void RegFile::setMiscReg(int miscReg, const MiscReg &val,
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ThreadContext * tc)
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{
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miscRegFile.setReg(miscReg, val, tc);
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}
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FloatReg RegFile::readFloatReg(int floatReg, int width)
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{
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return floatRegFile.readReg(floatReg, width);
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}
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FloatReg RegFile::readFloatReg(int floatReg)
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{
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//Use the "natural" width of a single float
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return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
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}
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FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
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{
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return floatRegFile.readRegBits(floatReg, width);
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}
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FloatRegBits RegFile::readFloatRegBits(int floatReg)
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{
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//Use the "natural" width of a single float
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return floatRegFile.readRegBits(floatReg,
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FloatRegFile::SingleWidth);
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}
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void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
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{
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floatRegFile.setReg(floatReg, val, width);
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}
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void RegFile::setFloatReg(int floatReg, const FloatReg &val)
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{
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//Use the "natural" width of a single float
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setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
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}
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void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
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{
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floatRegFile.setRegBits(floatReg, val, width);
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}
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void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
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{
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//Use the "natural" width of a single float
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floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
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}
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IntReg RegFile::readIntReg(int intReg)
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{
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return intRegFile.readReg(intReg);
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}
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void RegFile::setIntReg(int intReg, const IntReg &val)
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{
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intRegFile.setReg(intReg, val);
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}
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int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
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{
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int gl = tc->readMiscRegNoEffect(MISCREG_GL);
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int cwp = tc->readMiscRegNoEffect(MISCREG_CWP);
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//DPRINTF(Sparc, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
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int newReg;
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//The total number of global registers
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int numGlobals = (MaxGL + 1) * 8;
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if(reg < 8)
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{
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//Global register
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//Put it in the appropriate set of globals
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newReg = reg + gl * 8;
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}
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else if(reg < NumIntArchRegs)
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{
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//Regular windowed register
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//Put it in the window pointed to by cwp
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newReg = numGlobals +
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((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
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}
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else if(reg < NumIntArchRegs + NumMicroIntRegs)
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{
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//Microcode register
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//Displace from the end of the regular registers
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newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
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}
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else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
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{
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reg -= (NumIntArchRegs + NumMicroIntRegs);
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if(reg < 8)
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{
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//Global register from the next window
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//Put it in the appropriate set of globals
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newReg = reg + gl * 8;
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}
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else
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{
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//Windowed register from the previous window
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//Put it in the window before the one pointed to by cwp
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newReg = numGlobals +
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((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
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}
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}
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else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
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{
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reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
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if(reg < 8)
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{
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//Global register from the previous window
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//Put it in the appropriate set of globals
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newReg = reg + gl * 8;
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}
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else
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{
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//Windowed register from the next window
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//Put it in the window after the one pointed to by cwp
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newReg = numGlobals +
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((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
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}
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}
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else
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panic("Tried to flatten invalid register index %d!\n", reg);
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DPRINTF(Sparc, "Flattened register %d to %d.\n", reg, newReg);
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return newReg;
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//return intRegFile.flattenIndex(reg);
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}
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void RegFile::serialize(std::ostream &os)
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{
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intRegFile.serialize(os);
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floatRegFile.serialize(os);
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miscRegFile.serialize(os);
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SERIALIZE_SCALAR(pc);
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SERIALIZE_SCALAR(npc);
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SERIALIZE_SCALAR(nnpc);
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}
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void RegFile::unserialize(Checkpoint *cp, const std::string §ion)
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{
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intRegFile.unserialize(cp, section);
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floatRegFile.unserialize(cp, section);
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miscRegFile.unserialize(cp, section);
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(npc);
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UNSERIALIZE_SCALAR(nnpc);
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}
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void RegFile::changeContext(RegContextParam param, RegContextVal val)
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{
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switch(param)
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{
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case CONTEXT_CWP:
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intRegFile.setCWP(val);
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break;
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case CONTEXT_GLOBALS:
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intRegFile.setGlobals(val);
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break;
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default:
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panic("Tried to set illegal context parameter in the SPARC regfile.\n");
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}
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}
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void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
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{
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uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
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// Read all the trap level dependent registers and save them off
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for(int i = 1; i <= MaxTL; i++)
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{
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src->setMiscRegNoEffect(MISCREG_TL, i);
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dest->setMiscRegNoEffect(MISCREG_TL, i);
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dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT));
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dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC));
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dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC));
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dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE));
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}
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// Save off the traplevel
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dest->setMiscRegNoEffect(MISCREG_TL, tl);
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src->setMiscRegNoEffect(MISCREG_TL, tl);
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// ASRs
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// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y));
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// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR));
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dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI));
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dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
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dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS));
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dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT));
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dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
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dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK));
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dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
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// Priv Registers
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dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
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dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA));
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dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE));
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dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL));
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dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP));
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// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE));
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// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE));
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// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN));
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// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN));
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// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE));
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dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
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// Hyperprivilged registers
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dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE));
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dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP));
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dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA));
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dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
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src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
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dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
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src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
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// FSR
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dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR));
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//Strand Status Register
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dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
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src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
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// MMU Registers
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dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
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src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
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dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
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src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
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dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
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src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
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dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
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src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
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// Scratchpad Registers
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dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
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src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
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dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
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src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
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dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
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src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
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dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
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src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
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dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
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src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
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dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
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src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
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dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
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src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
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dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
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src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
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// Queue Registers
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dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
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src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
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dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
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src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
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dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
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src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
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dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
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src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
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dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
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src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
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dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
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src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
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dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
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src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
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dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
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src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
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}
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void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)
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{
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// First loop through the integer registers.
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for (int i = 0; i < TheISA::NumIntRegs; ++i) {
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dest->setIntReg(i, src->readIntReg(i));
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
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dest->setFloatRegBits(i, src->readFloatRegBits(i));
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}
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// Copy misc. registers
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copyMiscRegs(src, dest);
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// Lastly copy PC/NPC
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dest->setPC(src->readPC());
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dest->setNextPC(src->readNextPC());
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dest->setNextNPC(src->readNextNPC());
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}
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