272 lines
8.2 KiB
C++
272 lines
8.2 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_INSTS_MISC_HH__
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#define __ARCH_ARM_INSTS_MISC_HH__
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#include "arch/arm/insts/pred_inst.hh"
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class MrsOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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MrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest) :
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PredOp(mnem, _machInst, __opClass), dest(_dest)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class MsrBase : public PredOp
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{
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protected:
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uint8_t byteMask;
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MsrBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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uint8_t _byteMask) :
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PredOp(mnem, _machInst, __opClass), byteMask(_byteMask)
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{}
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void printMsrBase(std::ostream &os) const;
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};
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class MsrImmOp : public MsrBase
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{
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protected:
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uint32_t imm;
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MsrImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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uint32_t _imm, uint8_t _byteMask) :
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MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class MsrRegOp : public MsrBase
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{
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protected:
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IntRegIndex op1;
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MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _op1, uint8_t _byteMask) :
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MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class ImmOp : public PredOp
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{
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protected:
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uint64_t imm;
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ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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uint64_t _imm) :
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PredOp(mnem, _machInst, __opClass), imm(_imm)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegImmOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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uint64_t imm;
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RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, uint64_t _imm) :
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PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegRegOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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IntRegIndex op1;
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RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1) :
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PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegImmRegOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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uint64_t imm;
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IntRegIndex op1;
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RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), imm(_imm), op1(_op1)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegRegRegImmOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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IntRegIndex op1;
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IntRegIndex op2;
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uint64_t imm;
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RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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uint64_t _imm) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2), imm(_imm)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegRegRegRegOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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IntRegIndex op1;
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IntRegIndex op2;
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IntRegIndex op3;
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RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1,
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IntRegIndex _op2, IntRegIndex _op3) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2), op3(_op3)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegRegRegOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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IntRegIndex op1;
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IntRegIndex op2;
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RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegRegImmOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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IntRegIndex op1;
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uint64_t imm;
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RegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1,
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uint64_t _imm) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), imm(_imm)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegRegImmImmOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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IntRegIndex op1;
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uint64_t imm1;
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uint64_t imm2;
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RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1,
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uint64_t _imm1, uint64_t _imm2) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegImmRegShiftOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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uint64_t imm;
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IntRegIndex op1;
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int32_t shiftAmt;
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ArmShiftType shiftType;
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RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
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int32_t _shiftAmt, ArmShiftType _shiftType) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), imm(_imm), op1(_op1),
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shiftAmt(_shiftAmt), shiftType(_shiftType)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class UnknownOp : public PredOp
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{
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protected:
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UnknownOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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PredOp(mnem, _machInst, __opClass)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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#endif
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