364f6e3235
dev/sinic.cc:
dev/sinic.hh:
Fix sinic parameters. (header_bus -> io_bus)
python/m5/objects/Ethernet.mpy:
Add simobj definitions for sinic.
--HG--
extra : convert_revision : 77d5b80bd1f1708329b263fb48965d7f555cc9d1
121 lines
4.9 KiB
Text
121 lines
4.9 KiB
Text
from Device import DmaDevice
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from Pci import PciDevice
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simobj EtherInt(SimObject):
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type = 'EtherInt'
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abstract = True
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peer = Param.EtherInt(NULL, "peer interface")
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simobj EtherLink(SimObject):
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type = 'EtherLink'
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int1 = Param.EtherInt("interface 1")
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int2 = Param.EtherInt("interface 2")
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delay = Param.Latency('0us', "packet transmit delay")
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speed = Param.NetworkBandwidth('100Mbps', "link speed")
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dump = Param.EtherDump(NULL, "dump object")
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simobj EtherBus(SimObject):
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type = 'EtherBus'
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loopback = Param.Bool(True, "send packet back to the sending interface")
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dump = Param.EtherDump(NULL, "dump object")
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speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
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simobj EtherTap(EtherInt):
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type = 'EtherTap'
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bufsz = Param.Int(10000, "tap buffer size")
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dump = Param.EtherDump(NULL, "dump object")
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port = Param.UInt16(3500, "tap port")
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simobj EtherDump(SimObject):
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type = 'EtherDump'
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file = Param.String("dump file")
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simobj EtherDev(DmaDevice):
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type = 'EtherDev'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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dma_data_free = Param.Bool(False, "DMA of Data is free")
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
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dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
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dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
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dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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rx_filter = Param.Bool(True, "Enable Receive Filter")
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rx_delay = Param.Latency('1us', "Receive Delay")
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tx_delay = Param.Latency('1us', "Transmit Delay")
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intr_delay = Param.Latency('0us', "Interrupt Delay")
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payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
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physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
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tlaser = Param.Turbolaser(parent.any, "Turbolaser")
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simobj NSGigE(PciDevice):
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type = 'NSGigE'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
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dma_data_free = Param.Bool(False, "DMA of Data is free")
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
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dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
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dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
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dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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rx_filter = Param.Bool(True, "Enable Receive Filter")
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rx_delay = Param.Latency('1us', "Receive Delay")
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tx_delay = Param.Latency('1us', "Transmit Delay")
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rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
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tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
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m5reg = Param.UInt32(0, "Register for m5 usage")
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intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
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payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
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physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
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simobj EtherDevInt(EtherInt):
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type = 'EtherDevInt'
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device = Param.EtherDev("Ethernet device of this interface")
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simobj NSGigEInt(EtherInt):
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type = 'NSGigEInt'
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device = Param.NSGigE("Ethernet device of this interface")
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simobj Sinic(PciDevice):
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type = 'Sinic'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
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dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
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dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
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dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
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dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
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rx_filter = Param.Bool(True, "Enable Receive Filter")
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rx_delay = Param.Latency('1us', "Receive Delay")
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tx_delay = Param.Latency('1us', "Transmit Delay")
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rx_max_copy = Param.MemorySize('16kB', "rx max copy")
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tx_max_copy = Param.MemorySize('16kB', "tx max copy")
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rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo")
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tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo")
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rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold")
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tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold")
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intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
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payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
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physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
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simobj SinicInt(EtherInt):
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type = 'SinicInt'
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device = Param.Sinic("Ethernet device of this interface")
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