10c79efe55
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
365 lines
12 KiB
C++
365 lines
12 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Alpha Console Definition
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*/
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#include <cstddef>
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#include <cstdio>
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#include <string>
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "dev/alpha_console.hh"
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#include "dev/simconsole.hh"
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#include "dev/simple_disk.hh"
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#include "dev/tsunami_io.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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#include "sim/builder.hh"
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#include "sim/sim_object.hh"
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#include "sim/system.hh"
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using namespace std;
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AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
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System *s, BaseCPU *c, Platform *p,
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MemoryController *mmu, Addr a,
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HierParams *hier, Bus *pio_bus)
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: PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a)
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{
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mmu->add_child(this, RangeSize(addr, size));
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if (pio_bus) {
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pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
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&AlphaConsole::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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}
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alphaAccess = new Access;
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alphaAccess->last_offset = size - 1;
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alphaAccess->version = ALPHA_ACCESS_VERSION;
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alphaAccess->diskUnit = 1;
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alphaAccess->diskCount = 0;
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alphaAccess->diskPAddr = 0;
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alphaAccess->diskBlock = 0;
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alphaAccess->diskOperation = 0;
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alphaAccess->outputChar = 0;
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alphaAccess->inputChar = 0;
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alphaAccess->bootStrapImpure = 0;
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alphaAccess->bootStrapCPU = 0;
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alphaAccess->align2 = 0;
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system->setAlphaAccess(addr);
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}
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void
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AlphaConsole::startup()
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{
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alphaAccess->numCPUs = system->getNumCPUs();
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alphaAccess->kernStart = system->getKernelStart();
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alphaAccess->kernEnd = system->getKernelEnd();
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alphaAccess->entryPoint = system->getKernelEntry();
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alphaAccess->mem_size = system->physmem->size();
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alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
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alphaAccess->intrClockFrequency = platform->intrFrequency();
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}
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Fault *
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AlphaConsole::read(MemReqPtr &req, uint8_t *data)
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{
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memset(data, 0, req->size);
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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switch (req->size)
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{
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case sizeof(uint32_t):
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
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*(uint32_t*)data);
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switch (daddr)
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{
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case offsetof(AlphaAccess, last_offset):
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*(uint32_t*)data = alphaAccess->last_offset;
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break;
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case offsetof(AlphaAccess, version):
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*(uint32_t*)data = alphaAccess->version;
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break;
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case offsetof(AlphaAccess, numCPUs):
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*(uint32_t*)data = alphaAccess->numCPUs;
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break;
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case offsetof(AlphaAccess, bootStrapCPU):
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*(uint32_t*)data = alphaAccess->bootStrapCPU;
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break;
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case offsetof(AlphaAccess, intrClockFrequency):
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*(uint32_t*)data = alphaAccess->intrClockFrequency;
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break;
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default:
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// Old console code read in everyting as a 32bit int
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*(uint32_t*)data = *(uint32_t*)(consoleData + daddr);
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}
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break;
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case sizeof(uint64_t):
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
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*(uint64_t*)data);
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switch (daddr)
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{
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case offsetof(AlphaAccess, inputChar):
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*(uint64_t*)data = console->console_in();
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break;
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case offsetof(AlphaAccess, cpuClock):
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*(uint64_t*)data = alphaAccess->cpuClock;
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break;
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case offsetof(AlphaAccess, mem_size):
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*(uint64_t*)data = alphaAccess->mem_size;
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break;
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case offsetof(AlphaAccess, kernStart):
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*(uint64_t*)data = alphaAccess->kernStart;
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break;
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case offsetof(AlphaAccess, kernEnd):
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*(uint64_t*)data = alphaAccess->kernEnd;
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break;
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case offsetof(AlphaAccess, entryPoint):
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*(uint64_t*)data = alphaAccess->entryPoint;
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break;
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case offsetof(AlphaAccess, diskUnit):
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*(uint64_t*)data = alphaAccess->diskUnit;
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break;
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case offsetof(AlphaAccess, diskCount):
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*(uint64_t*)data = alphaAccess->diskCount;
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break;
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case offsetof(AlphaAccess, diskPAddr):
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*(uint64_t*)data = alphaAccess->diskPAddr;
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break;
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case offsetof(AlphaAccess, diskBlock):
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*(uint64_t*)data = alphaAccess->diskBlock;
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break;
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case offsetof(AlphaAccess, diskOperation):
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*(uint64_t*)data = alphaAccess->diskOperation;
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break;
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case offsetof(AlphaAccess, outputChar):
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*(uint64_t*)data = alphaAccess->outputChar;
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break;
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case offsetof(AlphaAccess, bootStrapImpure):
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*(uint64_t*)data = alphaAccess->bootStrapImpure;
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break;
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default:
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panic("Unknown 64bit access, %#x\n", daddr);
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}
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break;
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default:
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return MachineCheckFault;
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}
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return NoFault;
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}
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Fault *
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AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
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{
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uint64_t val;
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switch (req->size) {
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case sizeof(uint32_t):
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val = *(uint32_t *)data;
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break;
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case sizeof(uint64_t):
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val = *(uint64_t *)data;
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break;
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default:
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return MachineCheckFault;
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}
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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ExecContext *other_xc;
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switch (daddr) {
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case offsetof(AlphaAccess, diskUnit):
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alphaAccess->diskUnit = val;
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break;
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case offsetof(AlphaAccess, diskCount):
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alphaAccess->diskCount = val;
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break;
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case offsetof(AlphaAccess, diskPAddr):
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alphaAccess->diskPAddr = val;
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break;
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case offsetof(AlphaAccess, diskBlock):
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alphaAccess->diskBlock = val;
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break;
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case offsetof(AlphaAccess, diskOperation):
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if (val == 0x13)
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disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
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alphaAccess->diskCount);
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else
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panic("Invalid disk operation!");
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break;
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case offsetof(AlphaAccess, outputChar):
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console->out((char)(val & 0xff));
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break;
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case offsetof(AlphaAccess, bootStrapImpure):
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alphaAccess->bootStrapImpure = val;
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break;
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case offsetof(AlphaAccess, bootStrapCPU):
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warn("%d: Trying to launch another CPU!", curTick);
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assert(val > 0 && "Must not access primary cpu");
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other_xc = req->xc->system->execContexts[val];
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other_xc->regs.intRegFile[16] = val;
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other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
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other_xc->regs.intRegFile[0] = val;
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other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
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other_xc->activate(); //Start the cpu
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break;
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default:
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return MachineCheckFault;
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}
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return NoFault;
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}
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Tick
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AlphaConsole::cacheAccess(MemReqPtr &req)
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{
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return curTick + 1000;
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}
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void
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AlphaConsole::Access::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(last_offset);
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SERIALIZE_SCALAR(version);
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SERIALIZE_SCALAR(numCPUs);
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SERIALIZE_SCALAR(mem_size);
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SERIALIZE_SCALAR(cpuClock);
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SERIALIZE_SCALAR(intrClockFrequency);
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SERIALIZE_SCALAR(kernStart);
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SERIALIZE_SCALAR(kernEnd);
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SERIALIZE_SCALAR(entryPoint);
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SERIALIZE_SCALAR(diskUnit);
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SERIALIZE_SCALAR(diskCount);
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SERIALIZE_SCALAR(diskPAddr);
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SERIALIZE_SCALAR(diskBlock);
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SERIALIZE_SCALAR(diskOperation);
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SERIALIZE_SCALAR(outputChar);
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SERIALIZE_SCALAR(inputChar);
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SERIALIZE_SCALAR(bootStrapImpure);
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SERIALIZE_SCALAR(bootStrapCPU);
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}
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void
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AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(last_offset);
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UNSERIALIZE_SCALAR(version);
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UNSERIALIZE_SCALAR(numCPUs);
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UNSERIALIZE_SCALAR(mem_size);
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UNSERIALIZE_SCALAR(cpuClock);
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UNSERIALIZE_SCALAR(intrClockFrequency);
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UNSERIALIZE_SCALAR(kernStart);
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UNSERIALIZE_SCALAR(kernEnd);
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UNSERIALIZE_SCALAR(entryPoint);
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UNSERIALIZE_SCALAR(diskUnit);
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UNSERIALIZE_SCALAR(diskCount);
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UNSERIALIZE_SCALAR(diskPAddr);
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UNSERIALIZE_SCALAR(diskBlock);
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UNSERIALIZE_SCALAR(diskOperation);
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UNSERIALIZE_SCALAR(outputChar);
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UNSERIALIZE_SCALAR(inputChar);
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UNSERIALIZE_SCALAR(bootStrapImpure);
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UNSERIALIZE_SCALAR(bootStrapCPU);
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}
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void
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AlphaConsole::serialize(ostream &os)
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{
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alphaAccess->serialize(os);
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}
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void
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AlphaConsole::unserialize(Checkpoint *cp, const std::string §ion)
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{
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alphaAccess->unserialize(cp, section);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
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SimObjectParam<SimConsole *> sim_console;
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SimObjectParam<SimpleDisk *> disk;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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SimObjectParam<System *> system;
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SimObjectParam<BaseCPU *> cpu;
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SimObjectParam<Platform *> platform;
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SimObjectParam<Bus*> pio_bus;
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Param<Tick> pio_latency;
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SimObjectParam<HierParams *> hier;
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END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
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BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
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INIT_PARAM(sim_console, "The Simulator Console"),
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INIT_PARAM(disk, "Simple Disk"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(system, "system object"),
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INIT_PARAM(cpu, "Processor"),
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INIT_PARAM(platform, "platform"),
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INIT_PARAM(pio_bus, "The IO Bus to attach to"),
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INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
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END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
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CREATE_SIM_OBJECT(AlphaConsole)
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{
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return new AlphaConsole(getInstanceName(), sim_console, disk,
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system, cpu, platform, mmu, addr, hier, pio_bus);
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}
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REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
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