gem5/src/arch/x86/miscregfile.cc
Gabe Black e410a925df X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
2007-08-04 20:12:54 -07:00

168 lines
6.3 KiB
C++

/*
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use of this software in source and binary forms,
* with or without modification, are permitted provided that the
* following conditions are met:
*
* The software must be used only for Non-Commercial Use which means any
* use which is NOT directed to receiving any direct monetary
* compensation for, or commercial advantage from such use. Illustrative
* examples of non-commercial use are academic research, personal study,
* teaching, education and corporate research & development.
* Illustrative examples of commercial use are distributing products for
* commercial advantage and providing services using the software for
* commercial advantage.
*
* If you wish to use this software or functionality therein that may be
* covered by patents for commercial use, please contact:
* Director of Intellectual Property Licensing
* Office of Strategy and Technology
* Hewlett-Packard Company
* 1501 Page Mill Road
* Palo Alto, California 94304
*
* Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. Redistributions
* in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution. Neither the name of
* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission. No right of
* sublicense is granted herewith. Derivatives of the software and
* output created using the software may be prepared, but only for
* Non-Commercial Uses. Derivatives of the software may be shared with
* others provided: (i) the others agree to abide by the list of
* conditions herein which includes the Non-Commercial Use restrictions;
* and (ii) such Derivatives of the software include the above copyright
* notice to acknowledge the contribution from this software where
* applicable, this list of conditions and the disclaimer below.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/miscregfile.hh"
#include "sim/serialize.hh"
using namespace X86ISA;
using namespace std;
class Checkpoint;
//These functions map register indices to names
string X86ISA::getMiscRegName(RegIndex index)
{
panic("No misc registers in x86 yet!\n");
}
void MiscRegFile::clear()
{
//When there are actually misc regs implemented, this will clear them
}
MiscReg MiscRegFile::readRegNoEffect(int miscReg)
{
switch(miscReg)
{
case MISCREG_CR1:
case MISCREG_CR5:
case MISCREG_CR6:
case MISCREG_CR7:
case MISCREG_CR9:
case MISCREG_CR10:
case MISCREG_CR11:
case MISCREG_CR12:
case MISCREG_CR13:
case MISCREG_CR14:
case MISCREG_CR15:
panic("Tried to read invalid control register %d\n", miscReg);
break;
}
return regVal[miscReg];
}
MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
{
return readRegNoEffect(miscReg);
}
void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
{
switch(miscReg)
{
case MISCREG_CR1:
case MISCREG_CR5:
case MISCREG_CR6:
case MISCREG_CR7:
case MISCREG_CR9:
case MISCREG_CR10:
case MISCREG_CR11:
case MISCREG_CR12:
case MISCREG_CR13:
case MISCREG_CR14:
case MISCREG_CR15:
panic("Tried to write invalid control register %d\n", miscReg);
break;
}
regVal[miscReg] = val;
}
void MiscRegFile::setReg(int miscReg,
const MiscReg &val, ThreadContext * tc)
{
setRegNoEffect(miscReg, val);
}
void MiscRegFile::serialize(std::ostream & os)
{
SERIALIZE_ARRAY(regVal, NumMiscRegs);
}
void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
{
UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
}