be28d96510
The following patches had unexpected interactions with the current upstream code and have been reverted for now: e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
108 lines
3.4 KiB
Python
108 lines
3.4 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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Import('*')
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SimObject('ClockedObject.py')
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SimObject('TickedObject.py')
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SimObject('Root.py')
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SimObject('ClockDomain.py')
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SimObject('VoltageDomain.py')
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SimObject('System.py')
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SimObject('DVFSHandler.py')
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SimObject('SubSystem.py')
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Source('arguments.cc')
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Source('async.cc')
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Source('backtrace_%s.cc' % env['BACKTRACE_IMPL'])
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Source('core.cc')
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Source('tags.cc')
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Source('cxx_config.cc')
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Source('cxx_manager.cc')
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Source('cxx_config_ini.cc')
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Source('debug.cc')
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Source('py_interact.cc', skip_no_python=True)
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Source('eventq.cc')
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Source('global_event.cc')
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Source('init.cc', skip_no_python=True)
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Source('init_signals.cc')
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Source('main.cc', main=True, skip_lib=True)
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Source('root.cc')
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Source('serialize.cc')
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Source('drain.cc')
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Source('sim_events.cc')
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Source('sim_object.cc')
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Source('sub_system.cc')
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Source('ticked_object.cc')
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Source('simulate.cc')
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Source('stat_control.cc')
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Source('stat_register.cc', skip_no_python=True)
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Source('clock_domain.cc')
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Source('voltage_domain.cc')
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Source('linear_solver.cc')
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Source('system.cc')
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Source('dvfs_handler.cc')
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Source('clocked_object.cc')
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if env['TARGET_ISA'] != 'null':
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SimObject('InstTracer.py')
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SimObject('Process.py')
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Source('faults.cc')
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Source('process.cc')
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Source('fd_entry.cc')
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Source('pseudo_inst.cc')
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Source('syscall_emul.cc')
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DebugFlag('Checkpoint')
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DebugFlag('Config')
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DebugFlag('CxxConfig')
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DebugFlag('Drain')
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DebugFlag('Event')
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DebugFlag('Fault')
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DebugFlag('Flow')
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DebugFlag('IPI')
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DebugFlag('IPR')
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DebugFlag('Interrupt')
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DebugFlag('Loader')
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DebugFlag('PseudoInst')
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DebugFlag('Stack')
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DebugFlag('SyscallBase')
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DebugFlag('SyscallVerbose')
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DebugFlag('TimeSync')
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DebugFlag('Thread')
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DebugFlag('Timer')
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DebugFlag('VtoPhys')
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DebugFlag('WorkItems')
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DebugFlag('ClockDomain')
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DebugFlag('VoltageDomain')
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DebugFlag('DVFS')
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CompoundFlag('SyscallAll', [ 'SyscallBase', 'SyscallVerbose'])
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