be28d96510
The following patches had unexpected interactions with the current upstream code and have been reverted for now: e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
77 lines
3.8 KiB
Python
77 lines
3.8 KiB
Python
# Copyright (c) 2012, 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Hansson
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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# Enumerate set of allowed power states that can be used by a clocked object.
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# The list is kept generic to express a base minimal set.
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# State definition :-
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# Undefined: Invalid state, no power state derived information is available.
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# On: The logic block is actively running and consuming dynamic and leakage
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# energy depending on the amount of processing required.
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# Clk_gated: The clock circuity within the block is gated to save dynamic
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# energy, the power supply to the block is still on and leakage
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# energy is being consumed by the block.
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# Sram_retention: The SRAMs within the logic blocks are pulled into retention
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# state to reduce leakage energy further.
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# Off: The logic block is power gated and is not consuming any energy.
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class PwrState(Enum): vals = ['UNDEFINED',
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'ON',
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'CLK_GATED',
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'SRAM_RETENTION',
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'OFF']
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class ClockedObject(SimObject):
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type = 'ClockedObject'
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abstract = True
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cxx_header = "sim/clocked_object.hh"
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# The clock domain this clocked object belongs to, inheriting the
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# parent's clock domain by default
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clk_domain = Param.ClockDomain(Parent.clk_domain, "Clock domain")
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# Provide initial power state, should ideally get redefined in startup
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# routine
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default_p_state = Param.PwrState("UNDEFINED", "Default Power State")
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p_state_clk_gate_min = Param.Latency('1ns', "Min value of the distribution")
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p_state_clk_gate_max = Param.Latency('1s', "Max value of the distribution")
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p_state_clk_gate_bins = Param.Unsigned('20',
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"# bins in clk gated distribution")
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