be28d96510
The following patches had unexpected interactions with the current upstream code and have been reverted for now: e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
211 lines
7.2 KiB
C++
211 lines
7.2 KiB
C++
/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Mitch Hayenga
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*/
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#include "debug/HWPrefetch.hh"
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#include "mem/cache/prefetch/queued.hh"
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#include "mem/cache/base.hh"
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QueuedPrefetcher::QueuedPrefetcher(const QueuedPrefetcherParams *p)
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: BasePrefetcher(p), queueSize(p->queue_size), latency(p->latency),
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queueSquash(p->queue_squash), queueFilter(p->queue_filter),
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cacheSnoop(p->cache_snoop), tagPrefetch(p->tag_prefetch)
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{
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}
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QueuedPrefetcher::~QueuedPrefetcher()
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{
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// Delete the queued prefetch packets
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for (DeferredPacket &p : pfq) {
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delete p.pkt->req;
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delete p.pkt;
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}
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}
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Tick
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QueuedPrefetcher::notify(const PacketPtr &pkt)
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{
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// Verify this access type is observed by prefetcher
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if (observeAccess(pkt)) {
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Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize - 1);
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bool is_secure = pkt->isSecure();
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// Squash queued prefetches if demand miss to same line
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if (queueSquash) {
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auto itr = pfq.begin();
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while (itr != pfq.end()) {
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if (itr->pkt->getAddr() == blk_addr &&
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itr->pkt->isSecure() == is_secure) {
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delete itr->pkt->req;
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delete itr->pkt;
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itr = pfq.erase(itr);
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} else {
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++itr;
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}
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}
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}
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// Calculate prefetches given this access
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std::vector<Addr> addresses;
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calculatePrefetch(pkt, addresses);
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// Queue up generated prefetches
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for (Addr pf_addr : addresses) {
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// Block align prefetch address
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pf_addr = pf_addr & ~(Addr)(blkSize - 1);
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pfIdentified++;
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DPRINTF(HWPrefetch, "Found a pf candidate addr: %#x, "
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"inserting into prefetch queue.\n", pf_addr);
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if (queueFilter && inPrefetch(pf_addr, is_secure)) {
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pfBufferHit++;
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DPRINTF(HWPrefetch, "Prefetch addr already in "
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"prefetch queue\n");
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continue;
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}
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if (cacheSnoop && (inCache(pf_addr, is_secure) ||
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inMissQueue(pf_addr, is_secure))) {
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pfInCache++;
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DPRINTF(HWPrefetch, "Dropping redundant in "
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"cache/MSHR prefetch addr:%#x\n", pf_addr);
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continue;
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}
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// Create a prefetch memory request
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Request *pf_req =
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new Request(pf_addr, blkSize, 0, masterId);
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if (is_secure) {
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pf_req->setFlags(Request::SECURE);
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}
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pf_req->taskId(ContextSwitchTaskId::Prefetcher);
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PacketPtr pf_pkt = new Packet(pf_req, MemCmd::HardPFReq);
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pf_pkt->allocate();
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if (pkt->req->hasContextId()) {
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pf_req->setThreadContext(pkt->req->contextId(),
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pkt->req->threadId());
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}
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if (tagPrefetch && pkt->req->hasPC()) {
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// Tag prefetch packet with accessing pc
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pf_pkt->req->setPC(pkt->req->getPC());
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}
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// Verify prefetch buffer space for request
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if (pfq.size() == queueSize) {
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pfRemovedFull++;
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PacketPtr old_pkt = pfq.begin()->pkt;
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DPRINTF(HWPrefetch, "Prefetch queue full, removing "
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"oldest packet addr: %#x", old_pkt->getAddr());
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delete old_pkt->req;
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delete old_pkt;
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pfq.pop_front();
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}
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Tick pf_time = curTick() + clockPeriod() * latency;
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DPRINTF(HWPrefetch, "Prefetch queued. "
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"addr:%#x tick:%lld.\n", pf_addr, pf_time);
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pfq.emplace_back(pf_time, pf_pkt);
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}
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}
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return pfq.empty() ? MaxTick : pfq.front().tick;
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}
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PacketPtr
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QueuedPrefetcher::getPacket()
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{
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DPRINTF(HWPrefetch, "Requesting a prefetch to issue.\n");
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if (pfq.empty()) {
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DPRINTF(HWPrefetch, "No hardware prefetches available.\n");
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return NULL;
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}
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PacketPtr pkt = pfq.begin()->pkt;
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pfq.pop_front();
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pfIssued++;
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assert(pkt != NULL);
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DPRINTF(HWPrefetch, "Generating prefetch for %#x.\n", pkt->getAddr());
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return pkt;
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}
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bool
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QueuedPrefetcher::inPrefetch(Addr address, bool is_secure) const
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{
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for (const DeferredPacket &dp : pfq) {
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if (dp.pkt->getAddr() == address &&
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dp.pkt->isSecure() == is_secure) return true;
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}
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return false;
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}
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void
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QueuedPrefetcher::regStats()
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{
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BasePrefetcher::regStats();
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pfIdentified
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.name(name() + ".pfIdentified")
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.desc("number of prefetch candidates identified");
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pfBufferHit
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.name(name() + ".pfBufferHit")
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.desc("number of redundant prefetches already in prefetch queue");
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pfInCache
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.name(name() + ".pfInCache")
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.desc("number of redundant prefetches already in cache/mshr dropped");
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pfRemovedFull
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.name(name() + ".pfRemovedFull")
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.desc("number of prefetches dropped due to prefetch queue size");
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pfSpanPage
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.name(name() + ".pfSpanPage")
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.desc("number of prefetches not generated due to page crossing");
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}
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