be28d96510
The following patches had unexpected interactions with the current upstream code and have been reverted for now: e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
136 lines
3.8 KiB
C++
136 lines
3.8 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include "base/intmath.hh"
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#include "base/trace.hh"
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#include "cpu/pred/btb.hh"
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#include "debug/Fetch.hh"
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DefaultBTB::DefaultBTB(unsigned _numEntries,
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unsigned _tagBits,
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unsigned _instShiftAmt)
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: numEntries(_numEntries),
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tagBits(_tagBits),
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instShiftAmt(_instShiftAmt)
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{
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DPRINTF(Fetch, "BTB: Creating BTB object.\n");
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if (!isPowerOf2(numEntries)) {
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fatal("BTB entries is not a power of 2!");
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}
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btb.resize(numEntries);
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for (unsigned i = 0; i < numEntries; ++i) {
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btb[i].valid = false;
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}
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idxMask = numEntries - 1;
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tagMask = (1 << tagBits) - 1;
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tagShiftAmt = instShiftAmt + floorLog2(numEntries);
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}
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void
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DefaultBTB::reset()
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{
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for (unsigned i = 0; i < numEntries; ++i) {
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btb[i].valid = false;
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}
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}
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inline
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unsigned
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DefaultBTB::getIndex(Addr instPC)
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{
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// Need to shift PC over by the word offset.
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return (instPC >> instShiftAmt) & idxMask;
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}
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inline
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Addr
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DefaultBTB::getTag(Addr instPC)
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{
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return (instPC >> tagShiftAmt) & tagMask;
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}
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bool
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DefaultBTB::valid(Addr instPC, ThreadID tid)
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{
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unsigned btb_idx = getIndex(instPC);
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Addr inst_tag = getTag(instPC);
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assert(btb_idx < numEntries);
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if (btb[btb_idx].valid
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&& inst_tag == btb[btb_idx].tag
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&& btb[btb_idx].tid == tid) {
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return true;
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} else {
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return false;
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}
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}
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// @todo Create some sort of return struct that has both whether or not the
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// address is valid, and also the address. For now will just use addr = 0 to
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// represent invalid entry.
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TheISA::PCState
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DefaultBTB::lookup(Addr instPC, ThreadID tid)
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{
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unsigned btb_idx = getIndex(instPC);
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Addr inst_tag = getTag(instPC);
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assert(btb_idx < numEntries);
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if (btb[btb_idx].valid
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&& inst_tag == btb[btb_idx].tag
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&& btb[btb_idx].tid == tid) {
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return btb[btb_idx].target;
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} else {
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return 0;
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}
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}
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void
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DefaultBTB::update(Addr instPC, const TheISA::PCState &target, ThreadID tid)
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{
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unsigned btb_idx = getIndex(instPC);
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assert(btb_idx < numEntries);
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btb[btb_idx].tid = tid;
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btb[btb_idx].valid = true;
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btb[btb_idx].target = target;
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btb[btb_idx].tag = getTag(instPC);
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}
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