fbdeb60316
This patch changes how the cache determines if snoops should be forwarded from the memory side to the CPU side. Instead of having a parameter, the cache now looks at the port connected on the CPU side, and if it is a snooping port, then snoops are forwarded. Less error prone, and less parameters to worry about. The patch also tidies up the CPU classes to ensure that their I-side port is not snooping by removing overrides to the snoop request handler, such that snoop requests will panic via the default MasterPort implement
172 lines
6 KiB
C++
172 lines
6 KiB
C++
/*
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* Copyright (c) 2012-2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andrew Bardsley
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*/
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/**
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* @file
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*
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* Top level definition of the Minor in-order CPU model
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*/
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#ifndef __CPU_MINOR_CPU_HH__
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#define __CPU_MINOR_CPU_HH__
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#include "cpu/minor/activity.hh"
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#include "cpu/minor/stats.hh"
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#include "cpu/base.hh"
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#include "cpu/simple_thread.hh"
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#include "params/MinorCPU.hh"
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namespace Minor
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{
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/** Forward declared to break the cyclic inclusion dependencies between
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* pipeline and cpu */
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class Pipeline;
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/** Minor will use the SimpleThread state for now */
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typedef SimpleThread MinorThread;
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};
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/**
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* MinorCPU is an in-order CPU model with four fixed pipeline stages:
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*
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* Fetch1 - fetches lines from memory
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* Fetch2 - decomposes lines into macro-op instructions
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* Decode - decomposes macro-ops into micro-ops
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* Execute - executes those micro-ops
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*
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* This pipeline is carried in the MinorCPU::pipeline object.
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* The exec_context interface is not carried by MinorCPU but by
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* Minor::ExecContext objects
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* created by Minor::Execute.
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*/
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class MinorCPU : public BaseCPU
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{
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protected:
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/** pipeline is a container for the clockable pipeline stage objects.
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* Elements of pipeline call TheISA to implement the model. */
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Minor::Pipeline *pipeline;
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public:
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/** Activity recording for pipeline. This belongs to Pipeline but
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* stages will access it through the CPU as the MinorCPU object
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* actually mediates idling behaviour */
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Minor::MinorActivityRecorder *activityRecorder;
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/** These are thread state-representing objects for this CPU. If
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* you need a ThreadContext for *any* reason, use
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* threads[threadId]->getTC() */
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std::vector<Minor::MinorThread *> threads;
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public:
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/** Provide a non-protected base class for Minor's Ports as derived
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* classes are created by Fetch1 and Execute */
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class MinorCPUPort : public MasterPort
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{
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public:
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/** The enclosing cpu */
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MinorCPU &cpu;
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public:
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MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
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: MasterPort(name_, &cpu_), cpu(cpu_)
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{ }
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};
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protected:
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/** Return a reference to the data port. */
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MasterPort &getDataPort() override;
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/** Return a reference to the instruction port. */
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MasterPort &getInstPort() override;
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public:
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MinorCPU(MinorCPUParams *params);
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~MinorCPU();
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public:
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/** Starting, waking and initialisation */
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void init() override;
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void startup() override;
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void wakeup(ThreadID tid) override;
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Addr dbg_vtophys(Addr addr);
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/** Processor-specific statistics */
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Minor::MinorStats stats;
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/** Stats interface from SimObject (by way of BaseCPU) */
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void regStats() override;
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/** Simple inst count interface from BaseCPU */
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Counter totalInsts() const override;
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Counter totalOps() const override;
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void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
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void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
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/** Serialize pipeline data */
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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/** Drain interface */
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DrainState drain() override;
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void drainResume() override;
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/** Signal from Pipeline that MinorCPU should signal that a drain
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* is complete and set its drainState */
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void signalDrainDone();
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void memWriteback() override;
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/** Switching interface from BaseCPU */
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void switchOut() override;
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void takeOverFrom(BaseCPU *old_cpu) override;
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/** Thread activation interface from BaseCPU. */
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void activateContext(ThreadID thread_id) override;
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void suspendContext(ThreadID thread_id) override;
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/** Interface for stages to signal that they have become active after
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* a callback or eventq event where the pipeline itself may have
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* already been idled. The stage argument should be from the
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* enumeration Pipeline::StageId */
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void wakeupOnEvent(unsigned int stage_id);
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};
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#endif /* __CPU_MINOR_CPU_HH__ */
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