331 lines
10 KiB
C++
331 lines
10 KiB
C++
/*
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* Copyright (c) 2009 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/rubytest/RubyTester.hh"
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#include "mem/physical.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "mem/ruby/system/RubyPort.hh"
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RubyPort::RubyPort(const Params *p)
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: MemObject(p)
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{
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m_version = p->version;
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assert(m_version != -1);
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physmem = p->physmem;
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m_controller = NULL;
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m_mandatory_q_ptr = NULL;
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m_request_cnt = 0;
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pio_port = NULL;
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physMemPort = NULL;
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}
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void
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RubyPort::init()
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{
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assert(m_controller != NULL);
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m_mandatory_q_ptr = m_controller->getMandatoryQueue();
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}
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Port *
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RubyPort::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "port") {
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return new M5Port(csprintf("%s-port%d", name(), idx), this);
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}
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if (if_name == "pio_port") {
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// ensure there is only one pio port
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assert(pio_port == NULL);
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pio_port = new PioPort(csprintf("%s-pio-port%d", name(), idx), this);
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return pio_port;
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}
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if (if_name == "physMemPort") {
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// RubyPort should only have one port to physical memory
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assert (physMemPort == NULL);
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physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this);
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return physMemPort;
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}
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if (if_name == "functional") {
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// Calls for the functional port only want to access
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// functional memory. Therefore, directly pass these calls
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// ports to physmem.
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assert(physmem != NULL);
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return physmem->getPort(if_name, idx);
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}
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return NULL;
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}
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RubyPort::PioPort::PioPort(const std::string &_name,
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RubyPort *_port)
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: SimpleTimingPort(_name, _port)
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{
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DPRINTF(Ruby, "creating port to ruby sequencer to cpu %s\n", _name);
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ruby_port = _port;
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}
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RubyPort::M5Port::M5Port(const std::string &_name,
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RubyPort *_port)
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: SimpleTimingPort(_name, _port)
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{
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DPRINTF(Ruby, "creating port from ruby sequcner to cpu %s\n", _name);
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ruby_port = _port;
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}
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Tick
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RubyPort::PioPort::recvAtomic(PacketPtr pkt)
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{
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panic("RubyPort::PioPort::recvAtomic() not implemented!\n");
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return 0;
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}
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Tick
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RubyPort::M5Port::recvAtomic(PacketPtr pkt)
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{
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panic("RubyPort::M5Port::recvAtomic() not implemented!\n");
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return 0;
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}
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bool
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RubyPort::PioPort::recvTiming(PacketPtr pkt)
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{
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// In FS mode, ruby memory will receive pio responses from devices
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// and it must forward these responses back to the particular CPU.
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DPRINTF(MemoryAccess, "Pio response for address %#x\n", pkt->getAddr());
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assert(pkt->isResponse());
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// First we must retrieve the request port from the sender State
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RubyPort::SenderState *senderState =
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safe_cast<RubyPort::SenderState *>(pkt->senderState);
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M5Port *port = senderState->port;
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assert(port != NULL);
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// pop the sender state from the packet
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pkt->senderState = senderState->saved;
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delete senderState;
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port->sendTiming(pkt);
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return true;
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}
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bool
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RubyPort::M5Port::recvTiming(PacketPtr pkt)
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{
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DPRINTF(MemoryAccess,
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"Timing access caught for address %#x\n", pkt->getAddr());
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//dsm: based on SimpleTimingPort::recvTiming(pkt);
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// The received packets should only be M5 requests, which should never
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// get nacked. There used to be code to hanldle nacks here, but
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// I'm pretty sure it didn't work correctly with the drain code,
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// so that would need to be fixed if we ever added it back.
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assert(pkt->isRequest());
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if (pkt->memInhibitAsserted()) {
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warn("memInhibitAsserted???");
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// snooper will supply based on copy of packet
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// still target's responsibility to delete packet
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delete pkt;
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return true;
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}
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// Save the port in the sender state object to be used later to
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// route the response
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pkt->senderState = new SenderState(this, pkt->senderState);
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// Check for pio requests and directly send them to the dedicated
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// pio port.
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if (!isPhysMemAddress(pkt->getAddr())) {
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assert(ruby_port->pio_port != NULL);
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DPRINTF(MemoryAccess,
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"Request for address 0x%#x is assumed to be a pio request\n",
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pkt->getAddr());
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return ruby_port->pio_port->sendTiming(pkt);
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}
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// For DMA and CPU requests, translate them to ruby requests before
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// sending them to our assigned ruby port.
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RubyRequestType type = RubyRequestType_NULL;
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// If valid, copy the pc to the ruby request
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Addr pc = 0;
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if (pkt->req->hasPC()) {
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pc = pkt->req->getPC();
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}
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if (pkt->isLLSC()) {
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if (pkt->isWrite()) {
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DPRINTF(MemoryAccess, "Issuing SC\n");
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type = RubyRequestType_Locked_Write;
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} else {
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DPRINTF(MemoryAccess, "Issuing LL\n");
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assert(pkt->isRead());
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type = RubyRequestType_Locked_Read;
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}
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} else {
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if (pkt->isRead()) {
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if (pkt->req->isInstFetch()) {
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type = RubyRequestType_IFETCH;
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} else {
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type = RubyRequestType_LD;
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}
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} else if (pkt->isWrite()) {
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type = RubyRequestType_ST;
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} else if (pkt->isReadWrite()) {
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// Fix me. This conditional will never be executed
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// because isReadWrite() is just an OR of isRead() and
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// isWrite(). Furthermore, just because the packet is a
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// read/write request does not necessary mean it is a
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// read-modify-write atomic operation.
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type = RubyRequestType_RMW_Write;
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} else {
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panic("Unsupported ruby packet type\n");
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}
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}
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RubyRequest ruby_request(pkt->getAddr(), pkt->getPtr<uint8_t>(),
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pkt->getSize(), pc, type,
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RubyAccessMode_Supervisor, pkt);
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// Submit the ruby request
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RequestStatus requestStatus = ruby_port->makeRequest(ruby_request);
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// If the request successfully issued or the SC request completed because
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// exclusive permission was lost, then we should return true.
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// Otherwise, we need to delete the senderStatus we just created and return
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// false.
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if ((requestStatus == RequestStatus_Issued) ||
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(requestStatus == RequestStatus_LlscFailed)) {
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// The communicate to M5 whether the SC command succeeded by seting the
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// packet's extra data.
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if (pkt->isLLSC() && pkt->isWrite()) {
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if (requestStatus == RequestStatus_LlscFailed) {
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DPRINTF(MemoryAccess, "SC failed and request completed\n");
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pkt->req->setExtraData(0);
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} else {
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pkt->req->setExtraData(1);
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}
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}
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return true;
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}
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DPRINTF(MemoryAccess,
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"Request for address #x did not issue because %s\n",
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pkt->getAddr(), RequestStatus_to_string(requestStatus));
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SenderState* senderState = safe_cast<SenderState*>(pkt->senderState);
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pkt->senderState = senderState->saved;
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delete senderState;
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return false;
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}
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void
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RubyPort::ruby_hit_callback(PacketPtr pkt)
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{
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// Retrieve the request port from the sender State
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RubyPort::SenderState *senderState =
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safe_cast<RubyPort::SenderState *>(pkt->senderState);
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M5Port *port = senderState->port;
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assert(port != NULL);
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// pop the sender state from the packet
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pkt->senderState = senderState->saved;
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delete senderState;
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port->hitCallback(pkt);
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}
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void
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RubyPort::M5Port::hitCallback(PacketPtr pkt)
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{
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bool needsResponse = pkt->needsResponse();
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DPRINTF(MemoryAccess, "Hit callback needs response %d\n", needsResponse);
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ruby_port->physMemPort->sendAtomic(pkt);
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// turn packet around to go back to requester if response expected
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if (needsResponse) {
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// sendAtomic() should already have turned packet into
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// atomic response
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assert(pkt->isResponse());
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DPRINTF(MemoryAccess, "Sending packet back over port\n");
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sendTiming(pkt);
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} else {
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delete pkt;
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}
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DPRINTF(MemoryAccess, "Hit callback done!\n");
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}
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bool
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RubyPort::M5Port::sendTiming(PacketPtr pkt)
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{
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schedSendTiming(pkt, curTick + 1); //minimum latency, must be > 0
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return true;
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}
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bool
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RubyPort::PioPort::sendTiming(PacketPtr pkt)
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{
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schedSendTiming(pkt, curTick + 1); //minimum latency, must be > 0
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return true;
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}
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bool
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RubyPort::M5Port::isPhysMemAddress(Addr addr)
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{
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AddrRangeList physMemAddrList;
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bool snoop = false;
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ruby_port->physMemPort->getPeerAddressRanges(physMemAddrList, snoop);
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for (AddrRangeIter iter = physMemAddrList.begin();
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iter != physMemAddrList.end();
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iter++) {
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if (addr >= iter->start && addr <= iter->end) {
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DPRINTF(MemoryAccess, "Request found in %#llx - %#llx range\n",
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iter->start, iter->end);
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return true;
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}
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}
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return false;
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}
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