170 lines
6.1 KiB
C++
170 lines
6.1 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
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#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
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#include <vector>
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#include "base/hashmap.hh"
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#include "mem/gems_common/Vector.hh"
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#include "mem/protocol/AccessPermission.hh"
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#include "mem/protocol/CacheMsg.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/protocol/MachineType.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/DataBlock.hh"
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/profiler/CacheProfiler.hh"
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#include "mem/ruby/recorder/CacheRecorder.hh"
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#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
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#include "mem/ruby/system/LRUPolicy.hh"
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#include "mem/ruby/system/PseudoLRUPolicy.hh"
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#include "mem/ruby/system/System.hh"
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#include "params/RubyCache.hh"
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#include "sim/sim_object.hh"
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class CacheMemory : public SimObject
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{
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public:
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typedef RubyCacheParams Params;
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CacheMemory(const Params *p);
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~CacheMemory();
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void init();
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// Public Methods
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void printConfig(ostream& out);
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// perform a cache access and see if we hit or not. Return true on a hit.
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bool tryCacheAccess(const Address& address, CacheRequestType type,
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DataBlock*& data_ptr);
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// similar to above, but doesn't require full access check
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bool testCacheAccess(const Address& address, CacheRequestType type,
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DataBlock*& data_ptr);
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// tests to see if an address is present in the cache
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bool isTagPresent(const Address& address) const;
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// Returns true if there is:
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// a) a tag match on this address or there is
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// b) an unused line in the same cache "way"
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bool cacheAvail(const Address& address) const;
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// find an unused entry and sets the tag appropriate for the address
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void allocate(const Address& address, AbstractCacheEntry* new_entry);
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// Explicitly free up this address
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void deallocate(const Address& address);
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// Returns with the physical address of the conflicting cache line
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Address cacheProbe(const Address& address) const;
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// looks an address up in the cache
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AbstractCacheEntry& lookup(const Address& address);
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const AbstractCacheEntry& lookup(const Address& address) const;
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// Get/Set permission of cache block
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AccessPermission getPermission(const Address& address) const;
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void changePermission(const Address& address, AccessPermission new_perm);
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int getLatency() const { return m_latency; }
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// Hook for checkpointing the contents of the cache
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void recordCacheContents(CacheRecorder& tr) const;
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void
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setAsInstructionCache(bool is_icache)
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{
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m_is_instruction_only_cache = is_icache;
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}
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// Set this address to most recently used
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void setMRU(const Address& address);
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void profileMiss(const CacheMsg & msg);
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void getMemoryValue(const Address& addr, char* value,
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unsigned int size_in_bytes);
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void setMemoryValue(const Address& addr, char* value,
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unsigned int size_in_bytes);
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void setLocked (const Address& addr, int context);
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void clearLocked (const Address& addr);
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bool isLocked (const Address& addr, int context);
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// Print cache contents
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void print(ostream& out) const;
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void printData(ostream& out) const;
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void clearStats() const;
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void printStats(ostream& out) const;
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private:
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// convert a Address to its location in the cache
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Index addressToCacheSet(const Address& address) const;
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// Given a cache tag: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int findTagInSet(Index line, const Address& tag) const;
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int findTagInSetIgnorePermissions(Index cacheSet,
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const Address& tag) const;
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// Private copy constructor and assignment operator
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CacheMemory(const CacheMemory& obj);
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CacheMemory& operator=(const CacheMemory& obj);
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private:
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const string m_cache_name;
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int m_latency;
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// Data Members (m_prefix)
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bool m_is_instruction_only_cache;
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bool m_is_data_only_cache;
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// The first index is the # of cache lines.
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// The second index is the the amount associativity.
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m5::hash_map<Address, int> m_tag_index;
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Vector<Vector<AbstractCacheEntry*> > m_cache;
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Vector<Vector<int> > m_locked;
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AbstractReplacementPolicy *m_replacementPolicy_ptr;
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CacheProfiler* m_profiler_ptr;
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int m_cache_size;
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string m_policy;
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int m_cache_num_sets;
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int m_cache_num_set_bits;
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int m_cache_assoc;
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};
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#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
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