409 lines
10 KiB
C++
409 lines
10 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Device module for modelling the National Semiconductor
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* DP83820 ethernet controller
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*/
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#ifndef __DEV_NS_GIGE_HH__
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#define __DEV_NS_GIGE_HH__
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#include "base/inet.hh"
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#include "base/statistics.hh"
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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#include "dev/io_device.hh"
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#include "dev/ns_gige_reg.h"
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#include "dev/pcidev.hh"
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#include "dev/pktfifo.hh"
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#include "mem/bus/bus.hh"
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#include "sim/eventq.hh"
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/**
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* Ethernet device registers
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*/
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struct dp_regs {
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uint32_t command;
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uint32_t config;
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uint32_t mear;
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uint32_t ptscr;
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uint32_t isr;
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uint32_t imr;
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uint32_t ier;
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uint32_t ihr;
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uint32_t txdp;
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uint32_t txdp_hi;
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uint32_t txcfg;
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uint32_t gpior;
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uint32_t rxdp;
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uint32_t rxdp_hi;
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uint32_t rxcfg;
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uint32_t pqcr;
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uint32_t wcsr;
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uint32_t pcr;
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uint32_t rfcr;
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uint32_t rfdr;
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uint32_t srr;
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uint32_t mibc;
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uint32_t vrcr;
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uint32_t vtcr;
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uint32_t vdr;
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uint32_t ccsr;
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uint32_t tbicr;
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uint32_t tbisr;
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uint32_t tanar;
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uint32_t tanlpar;
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uint32_t taner;
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uint32_t tesr;
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};
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struct dp_rom {
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/**
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* for perfect match memory.
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* the linux driver doesn't use any other ROM
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*/
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uint8_t perfectMatch[ETH_ADDR_LEN];
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};
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class IntrControl;
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class NSGigEInt;
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class PhysicalMemory;
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class BaseInterface;
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class HierParams;
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class Bus;
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class PciConfigAll;
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/**
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* NS DP82830 Ethernet device model
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*/
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class NSGigE : public PciDev
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{
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public:
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/** Transmit State Machine states */
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enum TxState
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{
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txIdle,
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txDescRefr,
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txDescRead,
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txFifoBlock,
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txFragRead,
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txDescWrite,
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txAdvance
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};
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/** Receive State Machine States */
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enum RxState
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{
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rxIdle,
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rxDescRefr,
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rxDescRead,
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rxFifoBlock,
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rxFragWrite,
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rxDescWrite,
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rxAdvance
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};
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enum DmaState
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{
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dmaIdle,
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dmaReading,
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dmaWriting,
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dmaReadWaiting,
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dmaWriteWaiting
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};
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private:
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Addr addr;
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static const Addr size = sizeof(dp_regs);
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protected:
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typedef std::deque<PacketPtr> pktbuf_t;
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typedef pktbuf_t::iterator pktiter_t;
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/** device register file */
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dp_regs regs;
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dp_rom rom;
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/** pci settings */
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bool ioEnable;
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#if 0
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bool memEnable;
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bool bmEnable;
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#endif
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/*** BASIC STRUCTURES FOR TX/RX ***/
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/* Data FIFOs */
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PacketFifo txFifo;
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PacketFifo rxFifo;
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/** various helper vars */
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PacketPtr txPacket;
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PacketPtr rxPacket;
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uint8_t *txPacketBufPtr;
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uint8_t *rxPacketBufPtr;
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uint32_t txXferLen;
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uint32_t rxXferLen;
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bool rxDmaFree;
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bool txDmaFree;
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/** DescCaches */
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ns_desc txDescCache;
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ns_desc rxDescCache;
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/* tx State Machine */
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TxState txState;
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bool txEnable;
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/** Current Transmit Descriptor Done */
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bool CTDD;
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/** halt the tx state machine after next packet */
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bool txHalt;
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/** ptr to the next byte in the current fragment */
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Addr txFragPtr;
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/** count of bytes remaining in the current descriptor */
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uint32_t txDescCnt;
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DmaState txDmaState;
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/** rx State Machine */
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RxState rxState;
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bool rxEnable;
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/** Current Receive Descriptor Done */
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bool CRDD;
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/** num of bytes in the current packet being drained from rxDataFifo */
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uint32_t rxPktBytes;
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/** halt the rx state machine after current packet */
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bool rxHalt;
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/** ptr to the next byte in current fragment */
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Addr rxFragPtr;
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/** count of bytes remaining in the current descriptor */
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uint32_t rxDescCnt;
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DmaState rxDmaState;
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bool extstsEnable;
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protected:
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Tick dmaReadDelay;
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Tick dmaWriteDelay;
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Tick dmaReadFactor;
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Tick dmaWriteFactor;
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void *rxDmaData;
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Addr rxDmaAddr;
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int rxDmaLen;
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bool doRxDmaRead();
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bool doRxDmaWrite();
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void rxDmaReadCopy();
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void rxDmaWriteCopy();
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void *txDmaData;
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Addr txDmaAddr;
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int txDmaLen;
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bool doTxDmaRead();
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bool doTxDmaWrite();
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void txDmaReadCopy();
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void txDmaWriteCopy();
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void rxDmaReadDone();
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friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
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EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
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void rxDmaWriteDone();
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friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
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EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
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void txDmaReadDone();
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friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
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EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
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void txDmaWriteDone();
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friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
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EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
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bool dmaDescFree;
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bool dmaDataFree;
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protected:
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Tick txDelay;
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Tick rxDelay;
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void txReset();
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void rxReset();
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void regsReset();
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void rxKick();
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Tick rxKickTick;
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typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
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friend class RxKickEvent;
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void txKick();
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Tick txKickTick;
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typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
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friend class TxKickEvent;
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/**
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* Retransmit event
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*/
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void transmit();
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void txEventTransmit()
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{
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transmit();
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if (txState == txFifoBlock)
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txKick();
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}
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typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
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friend class TxEvent;
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TxEvent txEvent;
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void txDump() const;
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void rxDump() const;
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/**
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* receive address filter
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*/
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bool rxFilterEnable;
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bool rxFilter(const PacketPtr &packet);
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bool acceptBroadcast;
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bool acceptMulticast;
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bool acceptUnicast;
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bool acceptPerfect;
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bool acceptArp;
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PhysicalMemory *physmem;
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/**
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* Interrupt management
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*/
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IntrControl *intctrl;
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void devIntrPost(uint32_t interrupts);
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void devIntrClear(uint32_t interrupts);
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void devIntrChangeMask();
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Tick intrDelay;
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Tick intrTick;
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bool cpuPendingIntr;
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void cpuIntrPost(Tick when);
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void cpuInterrupt();
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void cpuIntrClear();
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typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
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friend class IntrEvent;
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IntrEvent *intrEvent;
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NSGigEInt *interface;
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public:
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struct Params : public PciDev::Params
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{
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PhysicalMemory *pmem;
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HierParams *hier;
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Bus *header_bus;
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Bus *payload_bus;
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Tick intr_delay;
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Tick tx_delay;
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Tick rx_delay;
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Tick pio_latency;
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bool dma_desc_free;
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bool dma_data_free;
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Tick dma_read_delay;
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Tick dma_write_delay;
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Tick dma_read_factor;
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Tick dma_write_factor;
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bool rx_filter;
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Net::EthAddr eaddr;
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uint32_t tx_fifo_size;
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uint32_t rx_fifo_size;
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};
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NSGigE(Params *params);
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~NSGigE();
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const Params *params() const { return (const Params *)_params; }
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virtual void WriteConfig(int offset, int size, uint32_t data);
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virtual void ReadConfig(int offset, int size, uint8_t *data);
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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bool cpuIntrPending() const;
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void cpuIntrAck() { cpuIntrClear(); }
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bool recvPacket(PacketPtr packet);
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void transferDone();
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void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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public:
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void regStats();
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private:
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Stats::Scalar<> txBytes;
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Stats::Scalar<> rxBytes;
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Stats::Scalar<> txPackets;
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Stats::Scalar<> rxPackets;
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Stats::Scalar<> txIpChecksums;
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Stats::Scalar<> rxIpChecksums;
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Stats::Scalar<> txTcpChecksums;
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Stats::Scalar<> rxTcpChecksums;
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Stats::Scalar<> txUdpChecksums;
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Stats::Scalar<> rxUdpChecksums;
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Stats::Scalar<> descDmaReads;
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Stats::Scalar<> descDmaWrites;
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Stats::Scalar<> descDmaRdBytes;
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Stats::Scalar<> descDmaWrBytes;
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Stats::Formula txBandwidth;
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Stats::Formula rxBandwidth;
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Stats::Formula txPacketRate;
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Stats::Formula rxPacketRate;
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public:
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Tick cacheAccess(MemReqPtr &req);
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};
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/*
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* Ethernet Interface for an Ethernet Device
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*/
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class NSGigEInt : public EtherInt
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{
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private:
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NSGigE *dev;
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public:
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NSGigEInt(const std::string &name, NSGigE *d)
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: EtherInt(name), dev(d) { dev->setInterface(this); }
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virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
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virtual void sendDone() { dev->transferDone(); }
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};
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#endif // __DEV_NS_GIGE_HH__
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