21df09cf7a
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
830 lines
28 KiB
C++
830 lines
28 KiB
C++
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#include <string>
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#include "cpu/checker/cpu.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/ozone/cpu.hh"
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#include "cpu/ozone/ozone_impl.hh"
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#include "cpu/ozone/simple_impl.hh"
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#include "cpu/ozone/simple_params.hh"
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#include "mem/cache/base_cache.hh"
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#include "sim/builder.hh"
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#include "sim/process.hh"
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#include "sim/sim_object.hh"
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class DerivOzoneCPU : public OzoneCPU<OzoneImpl>
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{
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public:
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DerivOzoneCPU(SimpleParams *p)
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: OzoneCPU<OzoneImpl>(p)
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{ }
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};
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class SimpleOzoneCPU : public OzoneCPU<SimpleImpl>
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{
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public:
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SimpleOzoneCPU(SimpleParams *p)
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: OzoneCPU<SimpleImpl>(p)
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{ }
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};
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////////////////////////////////////////////////////////////////////////
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//
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// OzoneCPU Simulation Object
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//
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
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Param<int> clock;
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Param<int> numThreads;
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#if FULL_SYSTEM
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SimObjectParam<System *> system;
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Param<int> cpu_id;
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SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaDTB *> dtb;
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#else
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SimObjectVectorParam<Process *> workload;
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//SimObjectParam<PageTable *> page_table;
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#endif // FULL_SYSTEM
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SimObjectParam<FunctionalMemory *> mem;
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SimObjectParam<BaseCPU *> checker;
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Param<Counter> max_insts_any_thread;
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_all_threads;
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SimObjectParam<BaseCache *> icache;
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SimObjectParam<BaseCache *> dcache;
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Param<unsigned> cachePorts;
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Param<unsigned> width;
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Param<unsigned> frontEndWidth;
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Param<unsigned> backEndWidth;
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Param<unsigned> backEndSquashLatency;
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Param<unsigned> backEndLatency;
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Param<unsigned> maxInstBufferSize;
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Param<unsigned> numPhysicalRegs;
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Param<unsigned> maxOutstandingMemOps;
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Param<unsigned> decodeToFetchDelay;
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Param<unsigned> renameToFetchDelay;
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Param<unsigned> iewToFetchDelay;
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Param<unsigned> commitToFetchDelay;
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Param<unsigned> fetchWidth;
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Param<unsigned> renameToDecodeDelay;
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Param<unsigned> iewToDecodeDelay;
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Param<unsigned> commitToDecodeDelay;
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Param<unsigned> fetchToDecodeDelay;
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Param<unsigned> decodeWidth;
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Param<unsigned> iewToRenameDelay;
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Param<unsigned> commitToRenameDelay;
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Param<unsigned> decodeToRenameDelay;
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Param<unsigned> renameWidth;
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Param<unsigned> commitToIEWDelay;
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Param<unsigned> renameToIEWDelay;
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Param<unsigned> issueToExecuteDelay;
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Param<unsigned> issueWidth;
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Param<unsigned> executeWidth;
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Param<unsigned> executeIntWidth;
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Param<unsigned> executeFloatWidth;
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Param<unsigned> executeBranchWidth;
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Param<unsigned> executeMemoryWidth;
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Param<unsigned> iewToCommitDelay;
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Param<unsigned> renameToROBDelay;
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Param<unsigned> commitWidth;
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Param<unsigned> squashWidth;
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Param<unsigned> localPredictorSize;
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Param<unsigned> localCtrBits;
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Param<unsigned> localHistoryTableSize;
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Param<unsigned> localHistoryBits;
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Param<unsigned> globalPredictorSize;
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Param<unsigned> globalCtrBits;
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Param<unsigned> globalHistoryBits;
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Param<unsigned> choicePredictorSize;
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Param<unsigned> choiceCtrBits;
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Param<unsigned> BTBEntries;
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Param<unsigned> BTBTagSize;
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Param<unsigned> RASSize;
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Param<unsigned> LQEntries;
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Param<unsigned> SQEntries;
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Param<unsigned> LFSTSize;
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Param<unsigned> SSITSize;
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Param<unsigned> numPhysIntRegs;
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Param<unsigned> numPhysFloatRegs;
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Param<unsigned> numIQEntries;
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Param<unsigned> numROBEntries;
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Param<bool> decoupledFrontEnd;
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Param<int> dispatchWidth;
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Param<int> wbWidth;
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Param<unsigned> smtNumFetchingThreads;
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Param<std::string> smtFetchPolicy;
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Param<std::string> smtLSQPolicy;
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Param<unsigned> smtLSQThreshold;
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Param<std::string> smtIQPolicy;
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Param<unsigned> smtIQThreshold;
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Param<std::string> smtROBPolicy;
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Param<unsigned> smtROBThreshold;
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Param<std::string> smtCommitPolicy;
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Param<unsigned> instShiftAmt;
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Param<bool> defer_registration;
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Param<bool> function_trace;
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Param<Tick> function_trace_start;
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END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
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BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
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INIT_PARAM(clock, "clock speed"),
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INIT_PARAM(numThreads, "number of HW thread contexts"),
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#if FULL_SYSTEM
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INIT_PARAM(system, "System object"),
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM(itb, "Instruction translation buffer"),
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INIT_PARAM(dtb, "Data translation buffer"),
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#else
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INIT_PARAM(workload, "Processes to run"),
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// INIT_PARAM(page_table, "Page table"),
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#endif // FULL_SYSTEM
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INIT_PARAM_DFLT(mem, "Memory", NULL),
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INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
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INIT_PARAM_DFLT(max_insts_any_thread,
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"Terminate when any thread reaches this inst count",
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0),
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INIT_PARAM_DFLT(max_insts_all_threads,
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"Terminate when all threads have reached"
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"this inst count",
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0),
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INIT_PARAM_DFLT(max_loads_any_thread,
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"Terminate when any thread reaches this load count",
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0),
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INIT_PARAM_DFLT(max_loads_all_threads,
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"Terminate when all threads have reached this load"
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"count",
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0),
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INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
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INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
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INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
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INIT_PARAM_DFLT(width, "Width", 1),
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INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
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INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
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INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
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INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
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INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
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INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
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INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
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INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
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INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
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INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
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"delay"),
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INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
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INIT_PARAM(fetchWidth, "Fetch width"),
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INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
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INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
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"delay"),
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INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
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INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
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INIT_PARAM(decodeWidth, "Decode width"),
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INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
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"delay"),
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INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
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INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
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INIT_PARAM(renameWidth, "Rename width"),
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INIT_PARAM(commitToIEWDelay, "Commit to "
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"Issue/Execute/Writeback delay"),
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INIT_PARAM(renameToIEWDelay, "Rename to "
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"Issue/Execute/Writeback delay"),
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INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
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"to the IEW stage)"),
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INIT_PARAM(issueWidth, "Issue width"),
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INIT_PARAM(executeWidth, "Execute width"),
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INIT_PARAM(executeIntWidth, "Integer execute width"),
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INIT_PARAM(executeFloatWidth, "Floating point execute width"),
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INIT_PARAM(executeBranchWidth, "Branch execute width"),
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INIT_PARAM(executeMemoryWidth, "Memory execute width"),
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INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
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"delay"),
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INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
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INIT_PARAM(commitWidth, "Commit width"),
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INIT_PARAM(squashWidth, "Squash width"),
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INIT_PARAM(localPredictorSize, "Size of local predictor"),
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INIT_PARAM(localCtrBits, "Bits per counter"),
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INIT_PARAM(localHistoryTableSize, "Size of local history table"),
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INIT_PARAM(localHistoryBits, "Bits for the local history"),
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INIT_PARAM(globalPredictorSize, "Size of global predictor"),
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INIT_PARAM(globalCtrBits, "Bits per counter"),
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INIT_PARAM(globalHistoryBits, "Bits of history"),
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INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
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INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
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INIT_PARAM(BTBEntries, "Number of BTB entries"),
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INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
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INIT_PARAM(RASSize, "RAS size"),
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INIT_PARAM(LQEntries, "Number of load queue entries"),
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INIT_PARAM(SQEntries, "Number of store queue entries"),
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INIT_PARAM(LFSTSize, "Last fetched store table size"),
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INIT_PARAM(SSITSize, "Store set ID table size"),
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INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
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INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
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"registers"),
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INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
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INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
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INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
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INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
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INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
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INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
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INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
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INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
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INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
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INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
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INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
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INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
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INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
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INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
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INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
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INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
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INIT_PARAM(function_trace, "Enable function trace"),
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INIT_PARAM(function_trace_start, "Cycle to start function trace")
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END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
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CREATE_SIM_OBJECT(DerivOzoneCPU)
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{
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DerivOzoneCPU *cpu;
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#if FULL_SYSTEM
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// Full-system only supports a single thread for the moment.
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int actual_num_threads = 1;
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#else
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// In non-full-system mode, we infer the number of threads from
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// the workload if it's not explicitly specified.
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int actual_num_threads =
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numThreads.isValid() ? numThreads : workload.size();
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if (workload.size() == 0) {
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fatal("Must specify at least one workload!");
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}
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#endif
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SimpleParams *params = new SimpleParams;
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params->clock = clock;
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params->name = getInstanceName();
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params->numberOfThreads = actual_num_threads;
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#if FULL_SYSTEM
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params->system = system;
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params->cpu_id = cpu_id;
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params->itb = itb;
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params->dtb = dtb;
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#else
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params->workload = workload;
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// params->pTable = page_table;
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#endif // FULL_SYSTEM
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params->mem = mem;
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params->checker = checker;
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params->max_insts_any_thread = max_insts_any_thread;
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params->max_insts_all_threads = max_insts_all_threads;
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params->max_loads_any_thread = max_loads_any_thread;
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params->max_loads_all_threads = max_loads_all_threads;
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//
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// Caches
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//
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params->icacheInterface = icache ? icache->getInterface() : NULL;
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params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
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params->cachePorts = cachePorts;
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params->width = width;
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params->frontEndWidth = frontEndWidth;
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params->backEndWidth = backEndWidth;
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params->backEndSquashLatency = backEndSquashLatency;
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params->backEndLatency = backEndLatency;
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params->maxInstBufferSize = maxInstBufferSize;
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params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
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params->maxOutstandingMemOps = maxOutstandingMemOps;
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params->decodeToFetchDelay = decodeToFetchDelay;
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params->renameToFetchDelay = renameToFetchDelay;
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params->iewToFetchDelay = iewToFetchDelay;
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params->commitToFetchDelay = commitToFetchDelay;
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params->fetchWidth = fetchWidth;
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params->renameToDecodeDelay = renameToDecodeDelay;
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params->iewToDecodeDelay = iewToDecodeDelay;
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params->commitToDecodeDelay = commitToDecodeDelay;
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params->fetchToDecodeDelay = fetchToDecodeDelay;
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params->decodeWidth = decodeWidth;
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params->iewToRenameDelay = iewToRenameDelay;
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params->commitToRenameDelay = commitToRenameDelay;
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params->decodeToRenameDelay = decodeToRenameDelay;
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params->renameWidth = renameWidth;
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params->commitToIEWDelay = commitToIEWDelay;
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params->renameToIEWDelay = renameToIEWDelay;
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params->issueToExecuteDelay = issueToExecuteDelay;
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params->issueWidth = issueWidth;
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params->executeWidth = executeWidth;
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params->executeIntWidth = executeIntWidth;
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params->executeFloatWidth = executeFloatWidth;
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params->executeBranchWidth = executeBranchWidth;
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params->executeMemoryWidth = executeMemoryWidth;
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params->iewToCommitDelay = iewToCommitDelay;
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params->renameToROBDelay = renameToROBDelay;
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params->commitWidth = commitWidth;
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params->squashWidth = squashWidth;
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params->localPredictorSize = localPredictorSize;
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params->localCtrBits = localCtrBits;
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params->localHistoryTableSize = localHistoryTableSize;
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params->localHistoryBits = localHistoryBits;
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params->globalPredictorSize = globalPredictorSize;
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params->globalCtrBits = globalCtrBits;
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params->globalHistoryBits = globalHistoryBits;
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params->choicePredictorSize = choicePredictorSize;
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params->choiceCtrBits = choiceCtrBits;
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params->BTBEntries = BTBEntries;
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params->BTBTagSize = BTBTagSize;
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params->RASSize = RASSize;
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params->LQEntries = LQEntries;
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params->SQEntries = SQEntries;
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params->SSITSize = SSITSize;
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params->LFSTSize = LFSTSize;
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params->numPhysIntRegs = numPhysIntRegs;
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params->numPhysFloatRegs = numPhysFloatRegs;
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params->numIQEntries = numIQEntries;
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params->numROBEntries = numROBEntries;
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params->decoupledFrontEnd = decoupledFrontEnd;
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params->dispatchWidth = dispatchWidth;
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params->wbWidth = wbWidth;
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params->smtNumFetchingThreads = smtNumFetchingThreads;
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params->smtFetchPolicy = smtFetchPolicy;
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params->smtIQPolicy = smtIQPolicy;
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params->smtLSQPolicy = smtLSQPolicy;
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params->smtLSQThreshold = smtLSQThreshold;
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params->smtROBPolicy = smtROBPolicy;
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params->smtROBThreshold = smtROBThreshold;
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params->smtCommitPolicy = smtCommitPolicy;
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params->instShiftAmt = 2;
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params->deferRegistration = defer_registration;
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params->functionTrace = function_trace;
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params->functionTraceStart = function_trace_start;
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cpu = new DerivOzoneCPU(params);
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return cpu;
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}
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REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU)
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////////////////////////////////////////////////////////////////////////
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//
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// OzoneCPU Simulation Object
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//
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
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Param<int> clock;
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Param<int> numThreads;
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#if FULL_SYSTEM
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SimObjectParam<System *> system;
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Param<int> cpu_id;
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|
SimObjectParam<AlphaITB *> itb;
|
|
SimObjectParam<AlphaDTB *> dtb;
|
|
#else
|
|
SimObjectVectorParam<Process *> workload;
|
|
//SimObjectParam<PageTable *> page_table;
|
|
#endif // FULL_SYSTEM
|
|
|
|
SimObjectParam<FunctionalMemory *> mem;
|
|
|
|
SimObjectParam<BaseCPU *> checker;
|
|
|
|
Param<Counter> max_insts_any_thread;
|
|
Param<Counter> max_insts_all_threads;
|
|
Param<Counter> max_loads_any_thread;
|
|
Param<Counter> max_loads_all_threads;
|
|
|
|
SimObjectParam<BaseCache *> icache;
|
|
SimObjectParam<BaseCache *> dcache;
|
|
|
|
Param<unsigned> cachePorts;
|
|
Param<unsigned> width;
|
|
Param<unsigned> frontEndWidth;
|
|
Param<unsigned> backEndWidth;
|
|
Param<unsigned> backEndSquashLatency;
|
|
Param<unsigned> backEndLatency;
|
|
Param<unsigned> maxInstBufferSize;
|
|
Param<unsigned> numPhysicalRegs;
|
|
|
|
Param<unsigned> decodeToFetchDelay;
|
|
Param<unsigned> renameToFetchDelay;
|
|
Param<unsigned> iewToFetchDelay;
|
|
Param<unsigned> commitToFetchDelay;
|
|
Param<unsigned> fetchWidth;
|
|
|
|
Param<unsigned> renameToDecodeDelay;
|
|
Param<unsigned> iewToDecodeDelay;
|
|
Param<unsigned> commitToDecodeDelay;
|
|
Param<unsigned> fetchToDecodeDelay;
|
|
Param<unsigned> decodeWidth;
|
|
|
|
Param<unsigned> iewToRenameDelay;
|
|
Param<unsigned> commitToRenameDelay;
|
|
Param<unsigned> decodeToRenameDelay;
|
|
Param<unsigned> renameWidth;
|
|
|
|
Param<unsigned> commitToIEWDelay;
|
|
Param<unsigned> renameToIEWDelay;
|
|
Param<unsigned> issueToExecuteDelay;
|
|
Param<unsigned> issueWidth;
|
|
Param<unsigned> executeWidth;
|
|
Param<unsigned> executeIntWidth;
|
|
Param<unsigned> executeFloatWidth;
|
|
Param<unsigned> executeBranchWidth;
|
|
Param<unsigned> executeMemoryWidth;
|
|
|
|
Param<unsigned> iewToCommitDelay;
|
|
Param<unsigned> renameToROBDelay;
|
|
Param<unsigned> commitWidth;
|
|
Param<unsigned> squashWidth;
|
|
|
|
Param<unsigned> localPredictorSize;
|
|
Param<unsigned> localCtrBits;
|
|
Param<unsigned> localHistoryTableSize;
|
|
Param<unsigned> localHistoryBits;
|
|
Param<unsigned> globalPredictorSize;
|
|
Param<unsigned> globalCtrBits;
|
|
Param<unsigned> globalHistoryBits;
|
|
Param<unsigned> choicePredictorSize;
|
|
Param<unsigned> choiceCtrBits;
|
|
|
|
Param<unsigned> BTBEntries;
|
|
Param<unsigned> BTBTagSize;
|
|
|
|
Param<unsigned> RASSize;
|
|
|
|
Param<unsigned> LQEntries;
|
|
Param<unsigned> SQEntries;
|
|
Param<unsigned> LFSTSize;
|
|
Param<unsigned> SSITSize;
|
|
|
|
Param<unsigned> numPhysIntRegs;
|
|
Param<unsigned> numPhysFloatRegs;
|
|
Param<unsigned> numIQEntries;
|
|
Param<unsigned> numROBEntries;
|
|
|
|
Param<bool> decoupledFrontEnd;
|
|
Param<int> dispatchWidth;
|
|
Param<int> wbWidth;
|
|
|
|
Param<unsigned> smtNumFetchingThreads;
|
|
Param<std::string> smtFetchPolicy;
|
|
Param<std::string> smtLSQPolicy;
|
|
Param<unsigned> smtLSQThreshold;
|
|
Param<std::string> smtIQPolicy;
|
|
Param<unsigned> smtIQThreshold;
|
|
Param<std::string> smtROBPolicy;
|
|
Param<unsigned> smtROBThreshold;
|
|
Param<std::string> smtCommitPolicy;
|
|
|
|
Param<unsigned> instShiftAmt;
|
|
|
|
Param<bool> defer_registration;
|
|
|
|
Param<bool> function_trace;
|
|
Param<Tick> function_trace_start;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
|
|
|
|
INIT_PARAM(clock, "clock speed"),
|
|
INIT_PARAM(numThreads, "number of HW thread contexts"),
|
|
|
|
#if FULL_SYSTEM
|
|
INIT_PARAM(system, "System object"),
|
|
INIT_PARAM(cpu_id, "processor ID"),
|
|
INIT_PARAM(itb, "Instruction translation buffer"),
|
|
INIT_PARAM(dtb, "Data translation buffer"),
|
|
#else
|
|
INIT_PARAM(workload, "Processes to run"),
|
|
// INIT_PARAM(page_table, "Page table"),
|
|
#endif // FULL_SYSTEM
|
|
|
|
INIT_PARAM_DFLT(mem, "Memory", NULL),
|
|
|
|
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
|
|
|
|
INIT_PARAM_DFLT(max_insts_any_thread,
|
|
"Terminate when any thread reaches this inst count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_insts_all_threads,
|
|
"Terminate when all threads have reached"
|
|
"this inst count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_loads_any_thread,
|
|
"Terminate when any thread reaches this load count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_loads_all_threads,
|
|
"Terminate when all threads have reached this load"
|
|
"count",
|
|
0),
|
|
|
|
INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
|
|
INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
|
|
|
|
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
|
|
INIT_PARAM_DFLT(width, "Width", 1),
|
|
INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
|
|
INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
|
|
INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
|
|
INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
|
|
INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
|
|
INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
|
|
|
|
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
|
|
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
|
|
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
|
|
"delay"),
|
|
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
|
|
INIT_PARAM(fetchWidth, "Fetch width"),
|
|
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
|
|
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
|
|
"delay"),
|
|
INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
|
|
INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
|
|
INIT_PARAM(decodeWidth, "Decode width"),
|
|
|
|
INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
|
|
"delay"),
|
|
INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
|
|
INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
|
|
INIT_PARAM(renameWidth, "Rename width"),
|
|
|
|
INIT_PARAM(commitToIEWDelay, "Commit to "
|
|
"Issue/Execute/Writeback delay"),
|
|
INIT_PARAM(renameToIEWDelay, "Rename to "
|
|
"Issue/Execute/Writeback delay"),
|
|
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
|
|
"to the IEW stage)"),
|
|
INIT_PARAM(issueWidth, "Issue width"),
|
|
INIT_PARAM(executeWidth, "Execute width"),
|
|
INIT_PARAM(executeIntWidth, "Integer execute width"),
|
|
INIT_PARAM(executeFloatWidth, "Floating point execute width"),
|
|
INIT_PARAM(executeBranchWidth, "Branch execute width"),
|
|
INIT_PARAM(executeMemoryWidth, "Memory execute width"),
|
|
|
|
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
|
|
"delay"),
|
|
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
|
|
INIT_PARAM(commitWidth, "Commit width"),
|
|
INIT_PARAM(squashWidth, "Squash width"),
|
|
|
|
INIT_PARAM(localPredictorSize, "Size of local predictor"),
|
|
INIT_PARAM(localCtrBits, "Bits per counter"),
|
|
INIT_PARAM(localHistoryTableSize, "Size of local history table"),
|
|
INIT_PARAM(localHistoryBits, "Bits for the local history"),
|
|
INIT_PARAM(globalPredictorSize, "Size of global predictor"),
|
|
INIT_PARAM(globalCtrBits, "Bits per counter"),
|
|
INIT_PARAM(globalHistoryBits, "Bits of history"),
|
|
INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
|
|
INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
|
|
|
|
INIT_PARAM(BTBEntries, "Number of BTB entries"),
|
|
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
|
|
|
|
INIT_PARAM(RASSize, "RAS size"),
|
|
|
|
INIT_PARAM(LQEntries, "Number of load queue entries"),
|
|
INIT_PARAM(SQEntries, "Number of store queue entries"),
|
|
INIT_PARAM(LFSTSize, "Last fetched store table size"),
|
|
INIT_PARAM(SSITSize, "Store set ID table size"),
|
|
|
|
INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
|
|
INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
|
|
"registers"),
|
|
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
|
|
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
|
|
|
|
INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
|
|
INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
|
|
INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
|
|
|
|
INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
|
|
INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
|
|
INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
|
|
INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
|
|
INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
|
|
INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
|
|
INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
|
|
INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
|
|
INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
|
|
|
|
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
|
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
|
|
|
INIT_PARAM(function_trace, "Enable function trace"),
|
|
INIT_PARAM(function_trace_start, "Cycle to start function trace")
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
|
|
|
|
CREATE_SIM_OBJECT(SimpleOzoneCPU)
|
|
{
|
|
SimpleOzoneCPU *cpu;
|
|
|
|
#if FULL_SYSTEM
|
|
// Full-system only supports a single thread for the moment.
|
|
int actual_num_threads = 1;
|
|
#else
|
|
// In non-full-system mode, we infer the number of threads from
|
|
// the workload if it's not explicitly specified.
|
|
int actual_num_threads =
|
|
numThreads.isValid() ? numThreads : workload.size();
|
|
|
|
if (workload.size() == 0) {
|
|
fatal("Must specify at least one workload!");
|
|
}
|
|
|
|
#endif
|
|
|
|
SimpleParams *params = new SimpleParams;
|
|
|
|
params->clock = clock;
|
|
|
|
params->name = getInstanceName();
|
|
params->numberOfThreads = actual_num_threads;
|
|
|
|
#if FULL_SYSTEM
|
|
params->system = system;
|
|
params->cpu_id = cpu_id;
|
|
params->itb = itb;
|
|
params->dtb = dtb;
|
|
#else
|
|
params->workload = workload;
|
|
// params->pTable = page_table;
|
|
#endif // FULL_SYSTEM
|
|
|
|
params->mem = mem;
|
|
params->checker = checker;
|
|
params->max_insts_any_thread = max_insts_any_thread;
|
|
params->max_insts_all_threads = max_insts_all_threads;
|
|
params->max_loads_any_thread = max_loads_any_thread;
|
|
params->max_loads_all_threads = max_loads_all_threads;
|
|
|
|
//
|
|
// Caches
|
|
//
|
|
params->icacheInterface = icache ? icache->getInterface() : NULL;
|
|
params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
|
|
params->cachePorts = cachePorts;
|
|
|
|
params->width = width;
|
|
params->frontEndWidth = frontEndWidth;
|
|
params->backEndWidth = backEndWidth;
|
|
params->backEndSquashLatency = backEndSquashLatency;
|
|
params->backEndLatency = backEndLatency;
|
|
params->maxInstBufferSize = maxInstBufferSize;
|
|
params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
|
|
|
|
params->decodeToFetchDelay = decodeToFetchDelay;
|
|
params->renameToFetchDelay = renameToFetchDelay;
|
|
params->iewToFetchDelay = iewToFetchDelay;
|
|
params->commitToFetchDelay = commitToFetchDelay;
|
|
params->fetchWidth = fetchWidth;
|
|
|
|
params->renameToDecodeDelay = renameToDecodeDelay;
|
|
params->iewToDecodeDelay = iewToDecodeDelay;
|
|
params->commitToDecodeDelay = commitToDecodeDelay;
|
|
params->fetchToDecodeDelay = fetchToDecodeDelay;
|
|
params->decodeWidth = decodeWidth;
|
|
|
|
params->iewToRenameDelay = iewToRenameDelay;
|
|
params->commitToRenameDelay = commitToRenameDelay;
|
|
params->decodeToRenameDelay = decodeToRenameDelay;
|
|
params->renameWidth = renameWidth;
|
|
|
|
params->commitToIEWDelay = commitToIEWDelay;
|
|
params->renameToIEWDelay = renameToIEWDelay;
|
|
params->issueToExecuteDelay = issueToExecuteDelay;
|
|
params->issueWidth = issueWidth;
|
|
params->executeWidth = executeWidth;
|
|
params->executeIntWidth = executeIntWidth;
|
|
params->executeFloatWidth = executeFloatWidth;
|
|
params->executeBranchWidth = executeBranchWidth;
|
|
params->executeMemoryWidth = executeMemoryWidth;
|
|
|
|
params->iewToCommitDelay = iewToCommitDelay;
|
|
params->renameToROBDelay = renameToROBDelay;
|
|
params->commitWidth = commitWidth;
|
|
params->squashWidth = squashWidth;
|
|
|
|
|
|
params->localPredictorSize = localPredictorSize;
|
|
params->localCtrBits = localCtrBits;
|
|
params->localHistoryTableSize = localHistoryTableSize;
|
|
params->localHistoryBits = localHistoryBits;
|
|
params->globalPredictorSize = globalPredictorSize;
|
|
params->globalCtrBits = globalCtrBits;
|
|
params->globalHistoryBits = globalHistoryBits;
|
|
params->choicePredictorSize = choicePredictorSize;
|
|
params->choiceCtrBits = choiceCtrBits;
|
|
|
|
params->BTBEntries = BTBEntries;
|
|
params->BTBTagSize = BTBTagSize;
|
|
|
|
params->RASSize = RASSize;
|
|
|
|
params->LQEntries = LQEntries;
|
|
params->SQEntries = SQEntries;
|
|
|
|
params->SSITSize = SSITSize;
|
|
params->LFSTSize = LFSTSize;
|
|
|
|
params->numPhysIntRegs = numPhysIntRegs;
|
|
params->numPhysFloatRegs = numPhysFloatRegs;
|
|
params->numIQEntries = numIQEntries;
|
|
params->numROBEntries = numROBEntries;
|
|
|
|
params->decoupledFrontEnd = decoupledFrontEnd;
|
|
params->dispatchWidth = dispatchWidth;
|
|
params->wbWidth = wbWidth;
|
|
|
|
params->smtNumFetchingThreads = smtNumFetchingThreads;
|
|
params->smtFetchPolicy = smtFetchPolicy;
|
|
params->smtIQPolicy = smtIQPolicy;
|
|
params->smtLSQPolicy = smtLSQPolicy;
|
|
params->smtLSQThreshold = smtLSQThreshold;
|
|
params->smtROBPolicy = smtROBPolicy;
|
|
params->smtROBThreshold = smtROBThreshold;
|
|
params->smtCommitPolicy = smtCommitPolicy;
|
|
|
|
params->instShiftAmt = 2;
|
|
|
|
params->deferRegistration = defer_registration;
|
|
|
|
params->functionTrace = function_trace;
|
|
params->functionTraceStart = function_trace_start;
|
|
|
|
cpu = new SimpleOzoneCPU(params);
|
|
|
|
return cpu;
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("SimpleOzoneCPU", SimpleOzoneCPU)
|
|
|