bd367d4825
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/sparc/arguments.hh:
move Copy* to vport since it's generic for all the ISAs
src/arch/sparc/isa_traits.hh:
the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase
src/arch/sparc/pagetable.hh:
add a class for getting bits out of the TteTag
src/arch/sparc/remote_gdb.cc:
add 32bit support kinda.... If its 32 bit
src/arch/sparc/remote_gdb.hh:
Add 32bit register offsets too.
src/arch/sparc/tlb.cc:
cleanup generation of tsb pointers
src/arch/sparc/tlb.hh:
add function to return tsb pointers for an address
make lookup public so vtophys can use it
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
write vtophys for sparc
src/base/bitfield.hh:
return a mask of bits first->last
src/mem/vport.cc:
src/mem/vport.hh:
move Copy* here since it's ISA generic
--HG--
extra : convert_revision : c42c331e396c0d51a2789029d8e232fe66995d0f
125 lines
5 KiB
C++
125 lines
5 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#include <string>
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#include "arch/sparc/vtophys.hh"
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#include "arch/sparc/tlb.hh"
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#include "base/compiler.hh"
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#include "base/chunk_generator.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "mem/vport.hh"
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using namespace std;
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namespace SparcISA
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{
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Addr vtophys(Addr vaddr)
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{
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// In SPARC it's almost always impossible to turn a VA->PA w/o a context
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// The only times we can kinda do it are if we have a SegKPM mapping
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// and can find the real address in the tlb or we have a physical
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// adddress already (beacuse we are looking at the hypervisor)
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// Either case is rare, so we'll just panic.
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panic("vtophys() without context on SPARC largly worthless\n");
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M5_DUMMY_RETURN
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}
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Addr vtophys(ThreadContext *tc, Addr addr)
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{
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// Here we have many options and are really implementing something like
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// a fill handler to find the address since there isn't a multilevel
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// table for us to walk around.
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//
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// 1. We are currently hyperpriv, return the address unmodified
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// 2. The mmu is off return(ra->pa)
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// 3. We are currently priv, use ctx0* tsbs to find the page
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// 4. We are not priv, use ctxN0* tsbs to find the page
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// For all accesses we check the tlbs first since it's possible that
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// long standing pages (e.g. locked kernel mappings) won't be in the tsb
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uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
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bool hpriv = bits(tlbdata,0,0);
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//bool priv = bits(tlbdata,2,2);
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bool addr_mask = bits(tlbdata,3,3);
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bool data_real = !bits(tlbdata,5,5);
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bool inst_real = !bits(tlbdata,4,4);
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bool ctx_zero = bits(tlbdata,18,16) > 0;
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int part_id = bits(tlbdata,15,8);
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int pri_context = bits(tlbdata,47,32);
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//int sec_context = bits(tlbdata,63,48);
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FunctionalPort *mem = tc->getPhysPort();
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ITB* itb = tc->getITBPtr();
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DTB* dtb = tc->getDTBPtr();
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TlbEntry* tbe;
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PageTableEntry pte;
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Addr tsbs[4];
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Addr va_tag;
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TteTag ttetag;
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if (hpriv)
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return addr;
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if (addr_mask)
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addr = addr & VAddrAMask;
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tbe = dtb->lookup(addr, part_id, data_real, ctx_zero ? 0 : pri_context , false);
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if (tbe) goto foundtbe;
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tbe = itb->lookup(addr, part_id, inst_real, ctx_zero ? 0 : pri_context, false);
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if (tbe) goto foundtbe;
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// We didn't find it in the tlbs, so lets look at the TSBs
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dtb->GetTsbPtr(tc, addr, ctx_zero ? 0 : pri_context, tsbs);
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va_tag = bits(addr, 63, 22);
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for (int x = 0; x < 4; x++) {
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ttetag = betoh(mem->read<uint64_t>(tsbs[x]));
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if (ttetag.valid() && ttetag.va() == va_tag) {
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pte.populate(betoh(mem->read<uint64_t>(tsbs[x]) + sizeof(uint64_t)),
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PageTableEntry::sun4v); // I think it's sun4v at least!
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DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TTE\n", addr,
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pte.paddrMask() | addr & pte.sizeMask());
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goto foundpte;
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}
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}
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panic("couldn't translate %#x\n", addr);
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foundtbe:
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pte = tbe->pte;
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DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TLB\n", addr,
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pte.paddrMask() | addr & pte.sizeMask());
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foundpte:
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return pte.paddrMask() | addr & pte.sizeMask();
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}
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}
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