1134 lines
131 KiB
Plaintext
1134 lines
131 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.533148 # Number of seconds simulated
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sim_ticks 2533147650000 # Number of ticks simulated
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final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 55856 # Simulator instruction rate (inst/s)
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host_op_rate 71871 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2346171672 # Simulator tick rate (ticks/s)
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host_mem_usage 407620 # Number of bytes of host memory used
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host_seconds 1079.69 # Real time elapsed on the host
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sim_insts 60307315 # Number of instructions simulated
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sim_ops 77598799 # Number of ops (including micro ops) simulated
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system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory
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system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15096808 # Total number of read requests seen
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system.physmem.writeReqs 813112 # Total number of write requests seen
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system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 966195712 # Total number of bytes read from memory
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system.physmem.bytesWritten 52039168 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry
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system.physmem.totGap 2533146526000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 36 # Categorize read packet sizes
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system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 154564 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 2990994 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 59094 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 32632 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 32536 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests
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system.physmem.totBusLat 75482565000 # Total cycles spent in databus access
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system.physmem.totBankLat 16909805000 # Total cycles spent in bank access
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system.physmem.avgQLat 26047.29 # Average queueing delay per request
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system.physmem.avgBankLat 1120.11 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 32167.41 # Average memory access latency
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system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 3.14 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.19 # Average read queue length over time
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system.physmem.avgWrQLen 11.48 # Average write queue length over time
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system.physmem.readRowHits 15020221 # Number of row buffer hits during reads
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system.physmem.writeRowHits 793131 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes
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|
system.physmem.avgGap 159218.06 # Average gap between requests
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|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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|
system.cpu.branchPred.lookups 14676489 # Number of BP lookups
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|
system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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|
system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions.
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|
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
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|
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
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|
system.cpu.checker.dtb.read_hits 14987326 # DTB read hits
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|
system.cpu.checker.dtb.read_misses 7302 # DTB read misses
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|
system.cpu.checker.dtb.write_hits 11227680 # DTB write hits
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|
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
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|
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
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|
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
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|
system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB
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|
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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|
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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|
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
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|
system.cpu.checker.dtb.read_accesses 14994628 # DTB read accesses
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|
system.cpu.checker.dtb.write_accesses 11229869 # DTB write accesses
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system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
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|
system.cpu.checker.dtb.hits 26215006 # DTB hits
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|
system.cpu.checker.dtb.misses 9491 # DTB misses
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system.cpu.checker.dtb.accesses 26224497 # DTB accesses
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system.cpu.checker.itb.inst_hits 61481313 # ITB inst hits
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system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
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system.cpu.checker.itb.read_hits 0 # DTB read hits
|
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system.cpu.checker.itb.read_misses 0 # DTB read misses
|
|
system.cpu.checker.itb.write_hits 0 # DTB write hits
|
|
system.cpu.checker.itb.write_misses 0 # DTB write misses
|
|
system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
|
system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
|
|
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.checker.itb.inst_accesses 61485784 # ITB inst accesses
|
|
system.cpu.checker.itb.hits 61481313 # DTB hits
|
|
system.cpu.checker.itb.misses 4471 # DTB misses
|
|
system.cpu.checker.itb.accesses 61485784 # DTB accesses
|
|
system.cpu.checker.numCycles 77884604 # number of cpu cycles simulated
|
|
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 51394402 # DTB read hits
|
|
system.cpu.dtb.read_misses 64202 # DTB read misses
|
|
system.cpu.dtb.write_hits 11700782 # DTB write hits
|
|
system.cpu.dtb.write_misses 15842 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 51458604 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 11716624 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 63095184 # DTB hits
|
|
system.cpu.dtb.misses 80044 # DTB misses
|
|
system.cpu.dtb.accesses 63175228 # DTB accesses
|
|
system.cpu.itb.inst_hits 12330326 # ITB inst hits
|
|
system.cpu.itb.inst_misses 11351 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 4952 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 12341677 # ITB inst accesses
|
|
system.cpu.itb.hits 12330326 # DTB hits
|
|
system.cpu.itb.misses 11351 # DTB misses
|
|
system.cpu.itb.accesses 12341677 # DTB accesses
|
|
system.cpu.numCycles 471833351 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued
|
|
system.cpu.iq.rate 0.263486 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 220665 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 11561887 # Number of branches executed
|
|
system.cpu.iew.exec_stores 12212575 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.257603 # Inst execution rate
|
|
system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 47219839 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 147889914 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 60457696 # Number of instructions committed
|
|
system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27386450 # Number of memory references committed
|
|
system.cpu.commit.loads 15654440 # Number of loads committed
|
|
system.cpu.commit.membars 403595 # Number of memory barriers committed
|
|
system.cpu.commit.branches 9961299 # Number of branches committed
|
|
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 68854449 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 991256 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 242385214 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 202032533 # The number of ROB writes
|
|
system.cpu.timesIdled 1770643 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 60307315 # Number of Instructions Simulated
|
|
system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated
|
|
system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.127815 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 550300284 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 88460224 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 8330 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 30137587 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 831885 # number of misc regfile writes
|
|
system.cpu.icache.replacements 979919 # number of replacements
|
|
system.cpu.icache.tagsinuse 511.615669 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 11266751 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 980431 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 11.491631 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 511.615669 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 11266751 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 11266751 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 11266751 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 11266751 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 11266751 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 11266751 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1059755 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1059755 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1059755 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1059755 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1059755 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1059755 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13997065496 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 13997065496 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 13997065496 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 13997065496 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 13997065496 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 13997065496 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 12326506 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 12326506 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 12326506 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 12326506 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 12326506 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 12326506 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085974 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.085974 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.085974 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.085974 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.085974 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.085974 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.831523 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13207.831523 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13207.831523 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13207.831523 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 4420 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 15.136986 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79294 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 79294 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 79294 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 79294 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 79294 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 79294 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980461 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 980461 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 980461 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 980461 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 980461 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 980461 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11381703997 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 11381703997 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11381703997 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 11381703997 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11381703997 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 11381703997 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079541 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.079541 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.079541 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.522926 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.522926 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 64335 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 51343.588717 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1886166 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 129730 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 14.539166 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 2498200830000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 36928.997165 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 25.134248 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 8156.882895 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 6232.574061 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.563492 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000384 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.124464 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.095102 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.783441 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53181 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10674 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 967006 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 387028 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1417889 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 607515 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 607515 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 112907 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 112907 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 53181 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 10674 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 967006 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 499935 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1530796 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 53181 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 10674 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 967006 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 499935 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1530796 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 12329 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 10702 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 23074 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 133200 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 133200 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 12329 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 143902 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 156274 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 12329 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 143902 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 156274 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2844500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 695710500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 632225999 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1330898999 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 476500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6732832500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6732832500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2844500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 695710500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7365058499 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 8063731499 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2844500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 695710500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7365058499 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 8063731499 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53222 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10676 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 979335 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 397730 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1440963 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 607515 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 607515 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 10 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246107 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 246107 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53222 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 10676 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 979335 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 643837 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1687070 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53222 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 10676 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 979335 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 643837 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1687070 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000770 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000187 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012589 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026908 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.016013 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985488 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985488 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.300000 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.300000 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541228 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541228 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000770 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000187 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012589 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.223507 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.092630 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000770 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000187 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012589 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.223507 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.092630 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69378.048780 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56428.785790 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59075.499813 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 57679.596039 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.184932 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.184932 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50546.790541 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50546.790541 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69378.048780 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56428.785790 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51181.071139 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 51599.955840 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69378.048780 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56428.785790 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51181.071139 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 51599.955840 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 59094 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 59094 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12316 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10640 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 22999 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133200 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 133200 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12316 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143840 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 156199 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12316 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143840 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 156199 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2335079 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93252 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541798119 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 497025991 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1041252441 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29202920 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29202920 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5072736540 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5072736540 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2335079 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93252 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541798119 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5569762531 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 6113988981 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2335079 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93252 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541798119 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5569762531 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 6113988981 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079407 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002423276 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007502683 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26890048041 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26890048041 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079407 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193892471317 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193897550724 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026752 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015961 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985488 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985488 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.300000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.300000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541228 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541228 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223411 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.092586 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223411 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.092586 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46626 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43991.402972 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46712.969079 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45273.813688 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38083.607658 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38083.607658 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 643325 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 21505081 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 643837 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 33.401437 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13751349 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13751349 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 7259815 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 7259815 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 243177 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 243177 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 247604 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 247604 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 21011164 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 21011164 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 21011164 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 21011164 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 737485 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 737485 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2962473 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2962473 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3699958 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3699958 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3699958 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3699958 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9781666500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 9781666500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 104377974730 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 104377974730 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180159500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 180159500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 114159641230 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 114159641230 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 114159641230 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 114159641230 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 14488834 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 14488834 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10222288 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 10222288 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256686 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 256686 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247614 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247614 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 24711122 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 24711122 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 24711122 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 24711122 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050900 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.050900 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289805 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.289805 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052629 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052629 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000040 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.149728 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.149728 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.149728 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.149728 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13263.546377 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13263.546377 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35233.392753 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 35233.392753 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13336.257310 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13336.257310 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16600 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16600 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 30854.307327 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 30854.307327 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 29793 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 16864 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 2613 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.401837 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 67.187251 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 607515 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 607515 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351842 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 351842 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713489 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 2713489 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1336 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1336 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3065331 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3065331 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3065331 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3065331 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385643 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 385643 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248984 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 248984 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12173 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12173 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 634627 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 634627 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 634627 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 634627 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4807486000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4807486000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182883413 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182883413 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140770000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140770000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12990369413 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 12990369413 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12990369413 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 12990369413 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395639500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395639500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36729406082 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36729406082 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219125045582 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 219125045582 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026617 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047424 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047424 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12466.156523 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12466.156523 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32865.097408 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32865.097408 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11564.117309 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11564.117309 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14600 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14600 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|