bd0c2d5b0b
This commit adds missing non-predicated, scalar floating point instructions. Specifically VRINT* floating point integer rounding instructions and VSEL* floating point conditional selects. Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
240 lines
8.4 KiB
C++
240 lines
8.4 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010-2013, 2016 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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vfpEnabledCheckCode = '''
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{
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Fault fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
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Cpsr, Cpacr, Nsacr, Fpexc,
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true, false);
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if (fault != NoFault)
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return fault;
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}
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'''
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vfp64EnabledCheckCode = '''
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{
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Fault fault = checkFPAdvSIMDEnabled64(xc->tcBase(), Cpsr, Cpacr64);
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if (fault != NoFault)
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return fault;
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}
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'''
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vmsrEnabledCheckCode = '''
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{
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Fault fault = NoFault;
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if (dest == (int)MISCREG_FPSCR) {
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fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
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Cpsr, Cpacr, Nsacr, Fpexc,
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true, false);
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} else if (!inPrivilegedMode(Cpsr)) {
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fault = disabledFault();
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} else {
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fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
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Cpsr, Cpacr, Nsacr, Fpexc,
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false, false);
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}
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if (fault != NoFault)
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return fault;
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}
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'''
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vmrsEnabledCheckCode = '''
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{
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Fault fault = NoFault;
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if (op1 == (int)MISCREG_FPSCR) {
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fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
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Cpsr, Cpacr, Nsacr, Fpexc,
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true, false);
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} else if (!inPrivilegedMode(Cpsr)) {
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fault = disabledFault();
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} else {
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fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(),
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Cpsr, Cpacr, Nsacr, Fpexc,
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false, false);
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}
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if (fault != NoFault)
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return fault;
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}
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'''
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}};
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def template FpRegRegOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1,
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VfpMicroMode mode = VfpNotAMicroop);
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%(BasicExecDeclare)s
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};
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}};
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def template FpRegRegOpConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1,
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VfpMicroMode mode)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, mode)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template FpRegImmOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
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uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
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%(BasicExecDeclare)s
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};
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}};
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def template FpRegImmOpConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _imm, mode)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template FpRegRegImmOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1,
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uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
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%(BasicExecDeclare)s
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};
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}};
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def template FpRegRegImmOpConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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uint64_t _imm,
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VfpMicroMode mode)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _imm, mode)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template FpRegRegRegOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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VfpMicroMode mode = VfpNotAMicroop);
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%(BasicExecDeclare)s
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};
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}};
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def template FpRegRegRegOpConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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IntRegIndex _op2,
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VfpMicroMode mode)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _op2, mode)
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{
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%(constructor)s;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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}
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}};
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def template FpRegRegRegCondOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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ConditionCode _cond,
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VfpMicroMode mode = VfpNotAMicroop);
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%(BasicExecDeclare)s
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};
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}};
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def template FpRegRegRegCondOpConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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IntRegIndex _op2,
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ConditionCode _cond,
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VfpMicroMode mode)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _op2, _cond, mode)
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{
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%(constructor)s;
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}
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}};
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