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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
Curtis Dunham bc7ab6970a stats: update references
2016-12-19 11:03:28 -06:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.829116 # Number of seconds simulated
sim_ticks 2829116273500 # Number of ticks simulated
final_tick 2829116273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 175307 # Simulator instruction rate (inst/s)
host_op_rate 212638 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4382427767 # Simulator tick rate (ticks/s)
host_mem_usage 587848 # Number of bytes of host memory used
host_seconds 645.56 # Real time elapsed on the host
sim_insts 113171321 # Number of instructions simulated
sim_ops 137270537 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1316000 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9472808 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 10791176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1316000 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1316000 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8091200 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::total 8108724 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 22814 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 148533 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 171384 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 126425 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::total 130806 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 339 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 465163 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3348328 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3814327 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 465163 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 465163 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2859974 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6194 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2866169 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2859974 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 465163 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3354522 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6680496 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 171385 # Number of read requests accepted
system.physmem.writeReqs 130806 # Number of write requests accepted
system.physmem.readBursts 171385 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 130806 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10959936 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue
system.physmem.bytesWritten 8121280 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10791240 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8108724 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10685 # Per bank write bursts
system.physmem.perBankRdBursts::1 10044 # Per bank write bursts
system.physmem.perBankRdBursts::2 10839 # Per bank write bursts
system.physmem.perBankRdBursts::3 10919 # Per bank write bursts
system.physmem.perBankRdBursts::4 13721 # Per bank write bursts
system.physmem.perBankRdBursts::5 10679 # Per bank write bursts
system.physmem.perBankRdBursts::6 11440 # Per bank write bursts
system.physmem.perBankRdBursts::7 11401 # Per bank write bursts
system.physmem.perBankRdBursts::8 10106 # Per bank write bursts
system.physmem.perBankRdBursts::9 10397 # Per bank write bursts
system.physmem.perBankRdBursts::10 10359 # Per bank write bursts
system.physmem.perBankRdBursts::11 9487 # Per bank write bursts
system.physmem.perBankRdBursts::12 10224 # Per bank write bursts
system.physmem.perBankRdBursts::13 11051 # Per bank write bursts
system.physmem.perBankRdBursts::14 10016 # Per bank write bursts
system.physmem.perBankRdBursts::15 9881 # Per bank write bursts
system.physmem.perBankWrBursts::0 8064 # Per bank write bursts
system.physmem.perBankWrBursts::1 7693 # Per bank write bursts
system.physmem.perBankWrBursts::2 8368 # Per bank write bursts
system.physmem.perBankWrBursts::3 8158 # Per bank write bursts
system.physmem.perBankWrBursts::4 8126 # Per bank write bursts
system.physmem.perBankWrBursts::5 8035 # Per bank write bursts
system.physmem.perBankWrBursts::6 8543 # Per bank write bursts
system.physmem.perBankWrBursts::7 8476 # Per bank write bursts
system.physmem.perBankWrBursts::8 7685 # Per bank write bursts
system.physmem.perBankWrBursts::9 7978 # Per bank write bursts
system.physmem.perBankWrBursts::10 7774 # Per bank write bursts
system.physmem.perBankWrBursts::11 7091 # Per bank write bursts
system.physmem.perBankWrBursts::12 7777 # Per bank write bursts
system.physmem.perBankWrBursts::13 8428 # Per bank write bursts
system.physmem.perBankWrBursts::14 7463 # Per bank write bursts
system.physmem.perBankWrBursts::15 7236 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 64 # Number of times write queue was full causing retry
system.physmem.totGap 2829116038500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 3002 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 167827 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 126425 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 150010 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 15012 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5351 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 860 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1779 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2636 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5595 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5997 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6586 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6402 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6748 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7868 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7605 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8603 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7681 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7236 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7368 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7248 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6733 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6856 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 562 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 481 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 407 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 306 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 283 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 252 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 302 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 240 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 207 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 230 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 153 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 176 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 61274 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 311.408036 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 184.010622 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.226456 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 22407 36.57% 36.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14885 24.29% 60.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6282 10.25% 71.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3692 6.03% 77.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2681 4.38% 81.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1694 2.76% 84.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1136 1.85% 86.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 990 1.62% 87.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7507 12.25% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 61274 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6334 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 27.026050 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 535.405637 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6332 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6334 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6334 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.033944 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.251538 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 14.603630 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5594 88.32% 88.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 89 1.41% 89.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 43 0.68% 90.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 45 0.71% 91.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 260 4.10% 95.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 21 0.33% 95.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 22 0.35% 95.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 12 0.19% 96.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 10 0.16% 96.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 11 0.17% 96.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 6 0.09% 96.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 5 0.08% 96.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 137 2.16% 98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 6 0.09% 98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 7 0.11% 98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 2 0.03% 98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 5 0.08% 99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.02% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 10 0.16% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 6 0.09% 99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.02% 99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 13 0.21% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 4 0.06% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.02% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 3 0.05% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.02% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 2 0.03% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.02% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.02% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 2 0.03% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 1 0.02% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6334 # Writes before turning the bus around for reads
system.physmem.totQLat 4767396000 # Total ticks spent queuing
system.physmem.totMemAccLat 7978314750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 856245000 # Total ticks spent in databus transfers
system.physmem.avgQLat 27838.81 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 46588.70 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.87 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.87 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.87 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 27.69 # Average write queue length when enqueuing
system.physmem.readRowHits 141756 # Number of row buffer hits during reads
system.physmem.writeRowHits 95114 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.94 # Row buffer hit rate for writes
system.physmem.avgGap 9362012.89 # Average gap between requests
system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 228894120 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 121660110 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 640657920 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 341716860 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 5259474480.000001 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 4230417450 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 318207360 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 10873180350 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 7365080640 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 667265125080 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 696646226220 # Total energy per rank (pJ)
system.physmem_0.averagePower 246.241638 # Core power per rank (mW)
system.physmem_0.totalIdleTime 2818840383250 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 582284750 # Time in different power states
system.physmem_0.memoryStateTime::REF 2236202000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 2775981781500 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 19179858500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 7291367000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 23844779750 # Time in different power states
system.physmem_1.actEnergy 208602240 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 110874720 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 582059940 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 320675040 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 5116263360.000001 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 4098436230 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 317114880 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 10121131470 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 7324658880 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 667774632810 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 695976520350 # Total energy per rank (pJ)
system.physmem_1.averagePower 246.004919 # Core power per rank (mW)
system.physmem_1.totalIdleTime 2819298070500 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 592691750 # Time in different power states
system.physmem_1.memoryStateTime::REF 2175820000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 2778027972250 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 19074668750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 7049691250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 22195429500 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu.branchPred.lookups 46888279 # Number of BP lookups
system.cpu.branchPred.condPredicted 24003428 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1174058 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 29505954 # Number of BTB lookups
system.cpu.branchPred.BTBHits 13539674 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 45.887938 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 11754876 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 34853 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 7941192 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 7796111 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 145081 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 60202 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 71258 # Table walker walks requested
system.cpu.dtb.walker.walksShort 71258 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29064 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23380 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 18814 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 52444 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 391.093357 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 2302.538664 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-4095 50603 96.49% 96.49% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::4096-8191 703 1.34% 97.83% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::8192-12287 574 1.09% 98.92% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::12288-16383 328 0.63% 99.55% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::16384-20479 67 0.13% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::24576-28671 32 0.06% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::28672-32767 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-36863 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::45056-49151 8 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 52444 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 16825 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 9444.665676 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 7665.862074 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 6497.692830 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-8191 8271 49.16% 49.16% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::8192-16383 6932 41.20% 90.36% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-24575 1364 8.11% 98.47% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::24576-32767 166 0.99% 99.45% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-40959 23 0.14% 99.59% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::40960-49151 60 0.36% 99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::90112-98303 2 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-106495 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::114688-122879 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 16825 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 118990825724 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.630270 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.488920 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 118944532224 99.96% 99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 32222000 0.03% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 6760000 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 4376000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 965500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 468000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 1159500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 331000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 11500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 118990825724 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6321 82.36% 82.36% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1354 17.64% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7675 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71258 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71258 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7675 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7675 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 78933 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 25423698 # DTB read hits
system.cpu.dtb.read_misses 61603 # DTB read misses
system.cpu.dtb.write_hits 19869004 # DTB write hits
system.cpu.dtb.write_misses 9655 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 365 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2214 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1308 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 25485301 # DTB read accesses
system.cpu.dtb.write_accesses 19878659 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 45292702 # DTB hits
system.cpu.dtb.misses 71258 # DTB misses
system.cpu.dtb.accesses 45363960 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 12656 # Table walker walks requested
system.cpu.itb.walker.walksShort 12656 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3345 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 1571 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 11085 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 575.732972 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 2511.318158 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-4095 10605 95.67% 95.67% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::4096-8191 108 0.97% 96.64% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::8192-12287 223 2.01% 98.66% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::12288-16383 110 0.99% 99.65% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::16384-20479 16 0.14% 99.79% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::20480-24575 18 0.16% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::40960-45055 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 11085 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 4896 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 9060.763889 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 7035.829304 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 11150.467524 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 4894 99.96% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 4896 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 24500602212 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.693564 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.461068 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 7508480500 30.65% 30.65% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 16991502712 69.35% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 619000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 24500602212 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 2990 89.92% 89.92% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 335 10.08% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3325 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12656 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 12656 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3325 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3325 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 15981 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 65983065 # ITB inst hits
system.cpu.itb.inst_misses 12656 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 3022 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 2179 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 65995721 # ITB inst accesses
system.cpu.itb.hits 65983065 # DTB hits
system.cpu.itb.misses 12656 # DTB misses
system.cpu.itb.accesses 65995721 # DTB accesses
system.cpu.numPwrStateTransitions 6078 # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples 3039 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean 886806915.729845 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev 17417893662.159683 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows 2967 97.63% 97.63% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 499972056544 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total 3039 # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON 134110056597 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2695006216903 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 268220171 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 105042564 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 183946336 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46888279 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33090661 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 151947545 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6066122 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 177459 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 8717 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 332750 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 861386 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 140 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 65981974 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 958405 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5944 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 261403622 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.858325 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.227883 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 162493227 62.16% 62.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 29157587 11.15% 73.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14046843 5.37% 78.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55705965 21.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 261403622 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.174813 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.685804 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 78158537 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 112446013 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64386093 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3839619 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2573360 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3404101 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 467760 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 157070559 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3511367 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2573360 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83910500 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 11255138 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 76381178 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62476128 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 24807318 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 146500137 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 914744 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 477372 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 65897 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 19059 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 22053744 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 150295383 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 677299800 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 164022340 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 11055 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 141831816 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 8463561 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2844179 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2649010 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13862871 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26349559 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 21216979 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1695969 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2055276 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143294681 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2116741 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 143114526 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 260917 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8140881 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14283010 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 121741 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 261403622 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.547485 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.874392 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 173098069 66.22% 66.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45413284 17.37% 83.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31798683 12.16% 95.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10270501 3.93% 99.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 823052 0.31% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 261403622 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 7334511 32.77% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5619720 25.11% 57.87% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 9419018 42.08% 99.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead 2403 0.01% 99.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite 8747 0.04% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 95906474 67.01% 67.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 114332 0.08% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 8541 0.01% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26136950 18.26% 85.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 20933494 14.63% 99.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead 2708 0.00% 99.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite 9690 0.01% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 143114526 # Type of FU issued
system.cpu.iq.rate 0.533571 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22384431 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.156409 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 570242068 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 153557534 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 140061190 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35954 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13312 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11500 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 165473068 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23552 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 325058 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1430930 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 739 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18590 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 619959 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 88583 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6407 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 2573360 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1161160 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 410961 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 145591536 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 26349559 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 21216979 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1093729 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17740 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 375076 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18590 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 276726 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 471114 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 747840 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 142217911 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25746602 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 825466 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 180114 # number of nop insts executed
system.cpu.iew.exec_refs 46577390 # number of memory reference insts executed
system.cpu.iew.exec_branches 26518344 # Number of branches executed
system.cpu.iew.exec_stores 20830788 # Number of stores executed
system.cpu.iew.exec_rate 0.530228 # Inst execution rate
system.cpu.iew.wb_sent 141848584 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 140072690 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63277897 # num instructions producing a value
system.cpu.iew.wb_consumers 95827474 # num instructions consuming a value
system.cpu.iew.wb_rate 0.522230 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660331 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 7357031 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1995000 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 714357 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 258509266 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.531607 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.132560 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 184931767 71.54% 71.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43412717 16.79% 88.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15465745 5.98% 94.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4363425 1.69% 96.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6516677 2.52% 98.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1538620 0.60% 99.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 797794 0.31% 99.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 415780 0.16% 99.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1066741 0.41% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 258509266 # Number of insts commited each cycle
system.cpu.commit.committedInsts 113326226 # Number of instructions committed
system.cpu.commit.committedOps 137425442 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 45515649 # Number of memory references committed
system.cpu.commit.loads 24918629 # Number of loads committed
system.cpu.commit.membars 814537 # Number of memory barriers committed
system.cpu.commit.branches 26054301 # Number of branches committed
system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions.
system.cpu.commit.int_insts 120244809 # Number of committed integer instructions.
system.cpu.commit.function_calls 4895095 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 91788341 66.79% 66.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 112911 0.08% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 8541 0.01% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 24915921 18.13% 85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20588240 14.98% 99.99% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite 8780 0.01% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 137425442 # Class of committed instruction
system.cpu.commit.bw_lim_events 1066741 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 379966373 # The number of ROB reads
system.cpu.rob.rob_writes 292446245 # The number of ROB writes
system.cpu.timesIdled 894795 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 6816549 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 5390012377 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113171321 # Number of Instructions Simulated
system.cpu.committedOps 137270537 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.370037 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.370037 # CPI: Total CPI of All Threads
system.cpu.ipc 0.421934 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.421934 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 155596425 # number of integer regfile reads
system.cpu.int_regfile_writes 88542209 # number of integer regfile writes
system.cpu.fp_regfile_reads 9690 # number of floating regfile reads
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
system.cpu.cc_regfile_reads 502428467 # number of cc regfile reads
system.cpu.cc_regfile_writes 53152553 # number of cc regfile writes
system.cpu.misc_regfile_reads 455632805 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521018 # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 835071 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.950856 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40080644 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 835583 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.967280 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 291735500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.950856 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999904 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999904 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 179195359 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179195359 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 23277723 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23277723 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15551809 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15551809 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 346190 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 346190 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441882 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441882 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460162 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460162 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 38829532 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38829532 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39175722 # number of overall hits
system.cpu.dcache.overall_hits::total 39175722 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 703752 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 703752 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3604950 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3604950 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 176883 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 176883 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 26584 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 26584 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 4308702 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4308702 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4485585 # number of overall misses
system.cpu.dcache.overall_misses::total 4485585 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11028419500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11028419500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 167321691201 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 167321691201 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 369201500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 369201500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 196000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 196000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 178350110701 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 178350110701 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 178350110701 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 178350110701 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23981475 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23981475 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19156759 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19156759 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523073 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 523073 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468466 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 468466 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460166 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460166 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 43138234 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43138234 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43661307 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43661307 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029346 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029346 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188182 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.188182 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338161 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.338161 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056747 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056747 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.099881 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.099881 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102736 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102736 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15670.889035 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15670.889035 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46414.427718 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 46414.427718 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13888.109389 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13888.109389 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 49000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 49000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41393.002046 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41393.002046 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39760.724789 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39760.724789 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 631534 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 7012 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 90.064746 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 693853 # number of writebacks
system.cpu.dcache.writebacks::total 693853 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291952 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 291952 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305716 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3305716 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18287 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 18287 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3597668 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3597668 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3597668 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3597668 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 411800 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 411800 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299234 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 299234 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119070 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 119070 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8297 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 711034 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 711034 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 830104 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 830104 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6169785000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6169785000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14920252482 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14920252482 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1648301500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1648301500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 125755000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 125755000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 192000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 192000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21090037482 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 21090037482 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22738338982 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 22738338982 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281915000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281915000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281915000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281915000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017172 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017172 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227636 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227636 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017711 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017711 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016483 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016483 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019012 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.019012 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14982.479359 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14982.479359 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49861.487939 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49861.487939 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13843.130092 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13843.130092 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15156.683138 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15156.683138 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 48000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 48000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29661.081583 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29661.081583 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27392.156865 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27392.156865 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201815.626305 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201815.626305 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106997.240722 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106997.240722 # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1888135 # number of replacements
system.cpu.icache.tags.tagsinuse 511.315248 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 63998090 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1888647 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 33.885681 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 14109342500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.315248 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.998663 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.998663 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 67867650 # Number of tag accesses
system.cpu.icache.tags.data_accesses 67867650 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 63998090 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 63998090 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 63998090 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 63998090 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 63998090 # number of overall hits
system.cpu.icache.overall_hits::total 63998090 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1980875 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1980875 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1980875 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1980875 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1980875 # number of overall misses
system.cpu.icache.overall_misses::total 1980875 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 27580080995 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 27580080995 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 27580080995 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 27580080995 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 27580080995 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 27580080995 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 65978965 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 65978965 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 65978965 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 65978965 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 65978965 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 65978965 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.030023 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.030023 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.030023 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.030023 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.030023 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.030023 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13923.180915 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13923.180915 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13923.180915 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13923.180915 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13923.180915 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13923.180915 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 2871 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 143 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 20.076923 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 1888135 # number of writebacks
system.cpu.icache.writebacks::total 1888135 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92189 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 92189 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 92189 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 92189 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 92189 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 92189 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1888686 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1888686 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1888686 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1888686 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1888686 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1888686 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 3009 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 3009 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24710647497 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 24710647497 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24710647497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 24710647497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24710647497 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 24710647497 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 246809500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 246809500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 246809500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 246809500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028626 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028626 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028626 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.028626 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028626 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.028626 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13083.512822 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13083.512822 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13083.512822 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13083.512822 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13083.512822 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13083.512822 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82023.762047 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82023.762047 # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 98088 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65152.227961 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5296727 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 163476 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 32.400640 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 91191447000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 8.773365 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.748453 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10408.912220 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 54730.793923 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000134 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158827 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.835126 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.994144 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65374 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5393 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59670 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997528 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 43909448 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 43909448 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52450 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9977 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 62427 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 693853 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 693853 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1850220 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1850220 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 2793 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 2793 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 161466 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 161466 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1868784 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1868784 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 525651 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 525651 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 52450 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 9977 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1868784 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 687117 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2618328 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 52450 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 9977 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1868784 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 687117 # number of overall hits
system.cpu.l2cache.overall_hits::total 2618328 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 15 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 22 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 135099 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 135099 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19840 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 19840 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13387 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 13387 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 15 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 19840 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 148486 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 168348 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 15 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 19840 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148486 # number of overall misses
system.cpu.l2cache.overall_misses::total 168348 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4526000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1704000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 6230000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 143500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 143500 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12744525000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12744525000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2137683500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2137683500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1563782000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1563782000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4526000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1704000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2137683500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 14308307000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 16452220500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4526000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1704000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2137683500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 14308307000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 16452220500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52465 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9984 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 62449 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 693853 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 693853 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1850220 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1850220 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2798 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2798 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 296565 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 296565 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1888624 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1888624 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 539038 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 539038 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52465 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 9984 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1888624 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 835603 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2786676 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52465 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 9984 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1888624 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 835603 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2786676 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000286 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000701 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001787 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001787 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455546 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.455546 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010505 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010505 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024835 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024835 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000286 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000701 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010505 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.177699 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060412 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000286 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000701 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010505 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.177699 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060412 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 301733.333333 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 243428.571429 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 283181.818182 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28700 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28700 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94334.710101 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94334.710101 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107746.144153 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107746.144153 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 116813.475760 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 116813.475760 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 301733.333333 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 243428.571429 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107746.144153 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96361.320259 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 97727.448500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 301733.333333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 243428.571429 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107746.144153 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96361.320259 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 97727.448500 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 90235 # number of writebacks
system.cpu.l2cache.writebacks::total 90235 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 113 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 138 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 15 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 22 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135099 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 135099 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19815 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19815 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13274 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13274 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 15 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 19815 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 148373 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 168210 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 15 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19815 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148373 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 168210 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34136 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61720 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4376000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 1634000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6010000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 93500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 93500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11393535000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11393535000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1937570500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1937570500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1419751500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1419751500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4376000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 1634000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1937570500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12813286500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 14756867000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4376000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1634000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1937570500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12813286500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14756867000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209196500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5892817000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6102013500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209196500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892817000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6102013500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000352 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001787 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001787 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455546 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455546 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010492 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024625 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024625 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177564 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060362 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177564 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060362 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 273181.818182 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18700 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18700 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84334.710101 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84334.710101 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97783.017916 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97783.017916 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 106957.322586 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 106957.322586 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97783.017916 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86358.613090 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87728.833006 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97783.017916 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86358.613090 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87728.833006 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189315.288977 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178755.961448 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100369.896612 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98866.064485 # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests 5482504 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758205 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46081 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 128785 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2556664 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 784088 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1888135 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 149071 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2798 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2802 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 296565 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 296565 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888686 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 539247 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5671462 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629463 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28809 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128289 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8458023 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241760656 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98078237 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 39936 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209860 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 340088689 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 135331 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 5917792 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 2986371 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.026284 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.159980 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2907876 97.37% 97.37% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 78495 2.63% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2986371 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5399114998 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 298125 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 2836925219 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1299904639 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 18830489 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 75878391 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30169 # Transaction distribution
system.iobus.trans_dist::ReadResp 30169 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178366 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480117 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 90500 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 648000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 6161000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 33823000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 187589137 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36712000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36410 # number of replacements
system.iocache.tags.tagsinuse 1.001834 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 253684759000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.001834 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062615 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062615 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 327996 # Number of tag accesses
system.iocache.tags.data_accesses 327996 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses
system.iocache.ReadReq_misses::total 220 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses
system.iocache.demand_misses::total 36444 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36444 # number of overall misses
system.iocache.overall_misses::total 36444 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 35729875 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 35729875 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4377211262 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4377211262 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 4412941137 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4412941137 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 4412941137 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4412941137 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 36444 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36444 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36444 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36444 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 162408.522727 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 162408.522727 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120837.325033 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120837.325033 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 121088.276177 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 121088.276177 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 121088.276177 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 121088.276177 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 444 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 222 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 36444 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 24729875 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 24729875 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2564234451 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2564234451 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 2588964326 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2588964326 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 2588964326 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2588964326 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112408.522727 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 112408.522727 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70788.274376 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70788.274376 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 71039.521622 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 71039.521622 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 71039.521622 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 71039.521622 # average overall mshr miss latency
system.membus.snoop_filter.tot_requests 339223 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 139296 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 511 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 34136 # Transaction distribution
system.membus.trans_dist::ReadResp 67466 # Transaction distribution
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
system.membus.trans_dist::WritebackDirty 126425 # Transaction distribution
system.membus.trans_dist::CleanEvict 8073 # Transaction distribution
system.membus.trans_dist::UpgradeReq 126 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 134978 # Transaction distribution
system.membus.trans_dist::ReadExResp 134978 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 33331 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 4572 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 449994 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557556 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72869 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72869 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 630425 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16582780 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16746157 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 19063277 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 5056 # Total snoops (count)
system.membus.snoopTraffic 30848 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 266381 # Request fanout histogram
system.membus.snoop_fanout::mean 0.019149 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.137050 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 261280 98.09% 98.09% # Request fanout histogram
system.membus.snoop_fanout::1 5101 1.91% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 266381 # Request fanout histogram
system.membus.reqLayer0.occupancy 84417000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1728499 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 876893413 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 984678000 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 5966654 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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