80d9be86e6
Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases.
100 lines
4 KiB
C++
Executable file
100 lines
4 KiB
C++
Executable file
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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* Jaidev Patwardhan
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*/
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#ifndef __ARCH_MIPS_PAGETABLE_H__
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#define __ARCH_MIPS_PAGETABLE_H__
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/utility.hh"
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#include "arch/mips/vtophys.hh"
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#include "config/full_system.hh"
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namespace MipsISA {
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struct VAddr
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{
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static const int ImplBits = 43;
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static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
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static const Addr UnImplMask = ~ImplMask;
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VAddr(Addr a) : addr(a) {}
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Addr addr;
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operator Addr() const { return addr; }
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const VAddr &operator=(Addr a) { addr = a; return *this; }
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Addr vpn() const { return (addr & ImplMask) >> PageShift; }
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Addr page() const { return addr & Page_Mask; }
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Addr offset() const { return addr & PageOffset; }
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Addr level3() const
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{ return MipsISA::PteAddr(addr >> PageShift); }
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Addr level2() const
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{ return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
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Addr level1() const
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{ return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
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};
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// ITB/DTB page table entry
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struct PTE
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{
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Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask)
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Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi)
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uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
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bool G; // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
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/* Contents of Entry Lo0 */
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Addr PFN0; // Physical Frame Number - Even
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bool D0; // Even entry Dirty Bit
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bool V0; // Even entry Valid Bit
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uint8_t C0; // Cache Coherency Bits - Even
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/* Contents of Entry Lo1 */
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Addr PFN1; // Physical Frame Number - Odd
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bool D1; // Odd entry Dirty Bit
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bool V1; // Odd entry Valid Bit
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uint8_t C1; // Cache Coherency Bits (3 bits)
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/* The next few variables are put in as optimizations to reduce TLB lookup overheads */
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/* For a given Mask, what is the address shift amount, and what is the OffsetMask */
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int AddrShiftAmount;
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int OffsetMask;
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bool Valid() { return (V0 | V1);};
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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};
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#endif // __ARCH_MIPS_PAGETABLE_H__
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