25e1b1c1f5
This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
1049 lines
119 KiB
Text
1049 lines
119 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.279557 # Number of seconds simulated
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sim_ticks 279556845500 # Number of ticks simulated
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final_tick 279556845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 180071 # Simulator instruction rate (inst/s)
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host_op_rate 180071 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 59759118 # Simulator tick rate (ticks/s)
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host_mem_usage 307148 # Number of bytes of host memory used
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host_seconds 4678.06 # Real time elapsed on the host
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sim_insts 842382029 # Number of instructions simulated
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sim_ops 842382029 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 176320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 18520448 # Number of bytes read from this memory
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system.physmem.bytes_read::total 18696768 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 176320 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 176320 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2755 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 289382 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 292137 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 630713 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 66249310 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 66880022 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 630713 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 630713 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 15265990 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 15265990 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 15265990 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 630713 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 66249310 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 82146012 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 292137 # Number of read requests accepted
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system.physmem.writeReqs 66683 # Number of write requests accepted
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system.physmem.readBursts 292137 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 18678144 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4265920 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 18696768 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 18015 # Per bank write bursts
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system.physmem.perBankRdBursts::1 18332 # Per bank write bursts
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system.physmem.perBankRdBursts::2 18407 # Per bank write bursts
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system.physmem.perBankRdBursts::3 18336 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18249 # Per bank write bursts
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system.physmem.perBankRdBursts::5 18230 # Per bank write bursts
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system.physmem.perBankRdBursts::6 18323 # Per bank write bursts
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system.physmem.perBankRdBursts::7 18299 # Per bank write bursts
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system.physmem.perBankRdBursts::8 18226 # Per bank write bursts
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system.physmem.perBankRdBursts::9 18222 # Per bank write bursts
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system.physmem.perBankRdBursts::10 18209 # Per bank write bursts
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system.physmem.perBankRdBursts::11 18393 # Per bank write bursts
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system.physmem.perBankRdBursts::12 18246 # Per bank write bursts
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system.physmem.perBankRdBursts::13 18127 # Per bank write bursts
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system.physmem.perBankRdBursts::14 18048 # Per bank write bursts
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system.physmem.perBankRdBursts::15 18184 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4160 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4142 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4099 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4180 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4149 # Per bank write bursts
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system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 279556756000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 292137 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 66683 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 215113 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 47042 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 29481 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 182 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 908 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 2144 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4025 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4146 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4061 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4201 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4139 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4069 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4085 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 4969 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 4178 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4054 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 4054 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4106 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4058 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 4471 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 4065 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 26 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 99332 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 230.959771 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 149.026626 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 277.596004 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 34426 34.66% 34.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 42079 42.36% 77.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 10100 10.17% 87.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 831 0.84% 88.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1119 1.13% 89.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 640 0.64% 89.79% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 198 0.20% 89.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1366 1.38% 91.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 8573 8.63% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 99332 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4052 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 69.011846 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 34.507282 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 732.804018 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 4044 99.80% 99.80% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::8192-9215 1 0.02% 99.85% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 4052 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 4052 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.449901 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.429330 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.841533 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 3145 77.62% 77.62% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 903 22.29% 99.90% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 1 0.02% 99.93% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 2 0.05% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 4052 # Writes before turning the bus around for reads
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system.physmem.totQLat 3589265250 # Total ticks spent queuing
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system.physmem.totMemAccLat 9061377750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1459230000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 12298.49 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 31048.49 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 66.81 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 15.26 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 66.88 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 15.27 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.64 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 24.19 # Average write queue length when enqueuing
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system.physmem.readRowHits 207190 # Number of row buffer hits during reads
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system.physmem.writeRowHits 51966 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 70.99 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 77.93 # Row buffer hit rate for writes
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system.physmem.avgGap 779100.26 # Average gap between requests
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system.physmem.pageHitRate 72.28 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 374756760 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 204480375 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 1139564400 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 18258829680 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 80335161315 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 97260556500 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 197789787510 # Total energy per rank (pJ)
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system.physmem_0.averagePower 707.529215 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 161282435500 # Time in different power states
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system.physmem_0.memoryStateTime::REF 9334780000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 108932951500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 375943680 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 205128000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1135750200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 215485920 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 18258829680 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 80056140615 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 97505311500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 197752589595 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 707.396151 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 161684152500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 9334780000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 108531075000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 192642813 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 125666016 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 11886398 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 146763457 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 126951211 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 86.500559 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 29013974 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 143 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 244534581 # DTB read hits
|
|
system.cpu.dtb.read_misses 309538 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 244844119 # DTB read accesses
|
|
system.cpu.dtb.write_hits 135677576 # DTB write hits
|
|
system.cpu.dtb.write_misses 31395 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 135708971 # DTB write accesses
|
|
system.cpu.dtb.data_hits 380212157 # DTB hits
|
|
system.cpu.dtb.data_misses 340933 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 380553090 # DTB accesses
|
|
system.cpu.itb.fetch_hits 197116758 # ITB hits
|
|
system.cpu.itb.fetch_misses 277 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 197117035 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 37 # Number of system calls
|
|
system.cpu.numCycles 559113692 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 202267120 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 1648589560 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 192642813 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 155965185 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 344477338 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 24241354 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 6562 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 197116758 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 7079440 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 558871871 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.949852 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.174628 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 239606568 42.87% 42.87% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 30232310 5.41% 48.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 22062681 3.95% 52.23% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 36416175 6.52% 58.75% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 68096392 12.18% 70.93% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 21641580 3.87% 74.80% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 19299985 3.45% 78.26% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 3539455 0.63% 78.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 117976725 21.11% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 558871871 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.344550 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.948577 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 168941255 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 91534254 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 273571884 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 12710570 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 12113908 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 15306458 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 6991 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 1583914254 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 25227 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 12113908 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 176800339 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 61738556 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 14140 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 278402636 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 29802292 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 1538072104 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 9577 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2573672 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 20322038 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 7208635 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 1027250775 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 1768837330 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 1729119220 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 39718109 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 388283617 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1370 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 9395851 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 372336921 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 175495034 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 40680070 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 11286315 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 1304559063 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 83 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 1015639240 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 8789930 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 462177116 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 427685030 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 558871871 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.817302 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.903889 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 199951896 35.78% 35.78% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 92994240 16.64% 52.42% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 91399550 16.35% 68.77% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 59708328 10.68% 79.46% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 56828177 10.17% 89.62% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 29755879 5.32% 94.95% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 17031836 3.05% 98.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 7177923 1.28% 99.28% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 4024042 0.72% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 558871871 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 2464205 10.45% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 15633751 66.29% 76.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 5485030 23.26% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 579358124 57.04% 57.04% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 7924 0.00% 57.04% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.04% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 13180764 1.30% 58.34% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.72% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 3339800 0.33% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 276992447 27.27% 86.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 138932359 13.68% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 1015639240 # Type of FU issued
|
|
system.cpu.iq.rate 1.816516 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 23582986 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.023220 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 2551718253 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 1725674688 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 939925074 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 70805014 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 41106869 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 34423614 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 1002860612 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 36360338 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 50469534 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 134826324 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1160001 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 45767 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 77193834 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2684 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 4171 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 12113908 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 60768232 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 187260 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 1479124792 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 20793 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 372336921 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 175495034 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 15841 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 182755 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 45767 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 11880363 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 16467 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 11896830 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 976089984 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 244844291 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 39549256 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 174565646 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 380553668 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 129052167 # Number of branches executed
|
|
system.cpu.iew.exec_stores 135709377 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.745781 # Inst execution rate
|
|
system.cpu.iew.wb_sent 974867255 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 974348688 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 556190036 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 832343662 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.742666 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.668222 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 543293982 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 11879630 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 486147412 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.910095 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.597279 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 208054375 42.80% 42.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 102342395 21.05% 63.85% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 51700065 10.63% 74.48% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 25702081 5.29% 79.77% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 21547094 4.43% 84.20% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 9129205 1.88% 86.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 10401484 2.14% 88.22% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 6670149 1.37% 89.59% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 50600564 10.41% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 486147412 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 928587628 # Number of instructions committed
|
|
system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 335811797 # Number of memory references committed
|
|
system.cpu.commit.loads 237510597 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 123111018 # Number of branches committed
|
|
system.cpu.commit.fp_insts 33436273 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 821934723 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 18524163 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 486529510 52.39% 61.68% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 7040 0.00% 61.68% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 237510597 25.58% 89.41% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 50600564 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 1904807320 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 3016488956 # The number of ROB writes
|
|
system.cpu.timesIdled 3196 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 241821 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 842382029 # Number of Instructions Simulated
|
|
system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.663729 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.663729 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.506638 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.506638 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 1237184723 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 705784215 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 36689750 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 24410793 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 777216 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4092.910211 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 289913128 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 781312 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 371.059357 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 371553500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.910211 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999246 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999246 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2498 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 253 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 585500596 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 585500596 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 192503314 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 192503314 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 97409790 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 97409790 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 24 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 24 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 289913104 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 289913104 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 289913104 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 289913104 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1555104 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1555104 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 891410 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 891410 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2446514 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2446514 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2446514 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2446514 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 83796204000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 83796204000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 61715896841 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 61715896841 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 145512100841 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 145512100841 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 145512100841 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 145512100841 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 194058418 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 194058418 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 292359618 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 292359618 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 292359618 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 292359618 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008014 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.008014 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009068 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.009068 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.008368 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.008368 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.008368 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.008368 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53884.630224 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 53884.630224 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69234.018960 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 69234.018960 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59477.321953 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 59477.321953 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59477.321953 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 59477.321953 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 22265 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 67906 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 515 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.164265 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 131.856311 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 88850 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 88850 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842619 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 842619 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 822583 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 822583 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1665202 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1665202 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1665202 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1665202 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712485 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 712485 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68827 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 68827 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 781312 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 781312 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 781312 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 781312 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24145312000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24145312000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5651970498 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5651970498 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29797282498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 29797282498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29797282498 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 29797282498 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33888.870643 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33888.870643 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82118.507243 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82118.507243 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38137.495006 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38137.495006 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38137.495006 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38137.495006 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 4695 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1651.888032 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 197108400 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 6404 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 30778.950656 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1651.888032 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.806586 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.806586 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 394239920 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 394239920 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 197108400 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 197108400 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 197108400 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 197108400 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 197108400 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 197108400 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 8358 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 8358 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 8358 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 8358 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 8358 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 8358 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 354830499 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 354830499 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 354830499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 354830499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 354830499 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 354830499 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 197116758 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 197116758 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 197116758 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 197116758 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 197116758 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 197116758 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42453.996052 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 42453.996052 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42453.996052 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 42453.996052 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42453.996052 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 42453.996052 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 620 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 56.363636 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1953 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1953 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1953 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 1953 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1953 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 1953 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6405 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 6405 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 6405 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 6405 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 6405 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 6405 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268250499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 268250499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268250499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 268250499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268250499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 268250499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41881.420609 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41881.420609 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41881.420609 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 41881.420609 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41881.420609 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 41881.420609 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 259359 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 32631.025486 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1208176 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 292097 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 4.136215 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 2513.776004 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 69.329948 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 30047.919535 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.076714 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002116 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.916990 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.995820 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32738 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 531 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5296 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26549 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999084 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 12917948 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 12917948 # Number of data accesses
|
|
system.cpu.l2cache.Writeback_hits::writebacks 88850 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 88850 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 2199 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 2199 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3649 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 3649 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 489731 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 489731 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 3649 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 491930 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 495579 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 3649 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 491930 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 495579 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66628 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66628 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2756 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 2756 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222754 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 222754 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2756 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 289382 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 292138 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2756 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 289382 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 292138 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5525354500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5525354500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 220303000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 220303000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17928202500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17928202500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 220303000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 23453557000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 23673860000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 220303000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 23453557000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 23673860000 # number of overall miss cycles
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 88850 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 88850 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 68827 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 68827 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6405 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 6405 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712485 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 712485 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 6405 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 781312 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 787717 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 6405 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 781312 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 787717 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.968050 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.968050 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.430289 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.430289 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312644 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312644 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.430289 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370380 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.370867 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.430289 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370380 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.370867 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82928.415981 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82928.415981 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79935.776488 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79935.776488 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80484.312291 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80484.312291 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79935.776488 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81047.048538 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 81036.564911 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79935.776488 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81047.048538 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 81036.564911 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 405 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 405 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66628 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66628 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2756 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2756 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222754 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222754 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2756 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 289382 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 292138 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2756 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 289382 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 292138 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4859074500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4859074500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 192753000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 192753000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15700662500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15700662500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192753000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20559737000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 20752490000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192753000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20559737000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 20752490000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.968050 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.968050 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.430289 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.430289 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312644 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312644 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430289 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370380 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.370867 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430289 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370380 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.370867 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72928.415981 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72928.415981 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69939.404935 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69939.404935 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70484.312291 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70484.312291 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69939.404935 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71047.048538 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71036.599142 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69939.404935 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71047.048538 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71036.599142 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 718889 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 155533 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 885737 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 68827 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 68827 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 6405 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712485 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17504 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339840 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 2357344 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 409856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55690368 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 56100224 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 259359 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 1828987 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.141805 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.348850 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 1569628 85.82% 85.82% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 259359 14.18% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 1828987 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 873664000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 9606000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1171968000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 225509 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 66683 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 191067 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 66628 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 66628 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 225509 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842024 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 842024 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22964480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 22964480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 549887 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 549887 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 549887 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 853984000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1551628500 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|