Gabe Black ec26f0bb3d Started adding a system to output data after every instruction. ... src/arch/alpha/regfile.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/cpu/exetrace.hh: Added functions to start to support dumping register values once per cycle. src/cpu/exetrace.cc: Added some code to support printing the value of registers after each cycle. src/python/m5/main.py: Options to turn on output after every instruction. They are commented out. --HG-- extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0		2006-08-11 20:21:35 -04:00
..
objects	Need config read/write latency.	2006-07-27 16:43:02 -04:00
__init__.py	Clean up some more config stuff.	2006-07-27 17:49:00 -04:00
attrdict.py	Migrate most of main() and and all option parsing to python	2006-07-10 23:00:13 -04:00
config.py	Merge ktlim@zizzer:/bk/newmem	2006-07-14 17:54:43 -04:00
convert.py	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
main.py	Started adding a system to output data after every instruction.	2006-08-11 20:21:35 -04:00
multidict.py	Only allow SimObject classes to be instantiated (no cloning!).	2006-06-10 19:58:36 -04:00
smartdict.py	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00