b7b545bc38
This change pulls the instruction decoding machinery (including caches) out of the StaticInst class and puts it into its own class. This has a few intrinsic benefits. First, the StaticInst code, which has gotten to be quite large, gets simpler. Second, the code that handles decode caching is now separated out into its own component and can be looked at in isolation, making it easier to understand. I took the opportunity to restructure the code a bit which will hopefully also help. Beyond that, this change also lays some ground work for each ISA to have its own, potentially stateful decode object. We'd be able to include less contextualizing information in the ExtMachInst objects since that context would be applied at the decoder. Also, the decoder could "know" ahead of time that all the instructions it's going to see are going to be, for instance, 64 bit mode, and it will have one less thing to check when it decodes them. Because the decode caching mechanism has been separated out, it's now possible to have multiple caches which correspond to different types of decoding context. Having one cache for each element of the cross product of different configurations may become prohibitive, so it may be desirable to clear out the cache when relatively static state changes and not to have one for each setting. Because the decode function is no longer universally accessible as a static member of the StaticInst class, a new function was added to the ThreadContexts that returns the applicable decode object.
192 lines
6.7 KiB
Python
192 lines
6.7 KiB
Python
# -*- mode:python -*-
|
|
|
|
# Copyright (c) 2006 The Regents of The University of Michigan
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions are
|
|
# met: redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer;
|
|
# redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution;
|
|
# neither the name of the copyright holders nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
#
|
|
# Authors: Steve Reinhardt
|
|
|
|
Import('*')
|
|
|
|
if env['TARGET_ISA'] == 'no':
|
|
Return()
|
|
|
|
#################################################################
|
|
#
|
|
# Generate StaticInst execute() method signatures.
|
|
#
|
|
# There must be one signature for each CPU model compiled in.
|
|
# Since the set of compiled-in models is flexible, we generate a
|
|
# header containing the appropriate set of signatures on the fly.
|
|
#
|
|
#################################################################
|
|
|
|
# Template for execute() signature.
|
|
exec_sig_template = '''
|
|
virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
|
|
virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
|
|
{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
|
|
virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
|
|
{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
|
|
virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
|
|
Trace::InstRecord *traceData) const
|
|
{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
|
|
'''
|
|
|
|
mem_ini_sig_template = '''
|
|
virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
|
|
{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
|
|
virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
|
|
'''
|
|
|
|
mem_comp_sig_template = '''
|
|
virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
|
|
'''
|
|
|
|
# Generate a temporary CPU list, including the CheckerCPU if
|
|
# it's enabled. This isn't used for anything else other than StaticInst
|
|
# headers.
|
|
temp_cpu_list = env['CPU_MODELS'][:]
|
|
|
|
if env['USE_CHECKER']:
|
|
temp_cpu_list.append('CheckerCPU')
|
|
SimObject('CheckerCPU.py')
|
|
|
|
# Generate header.
|
|
def gen_cpu_exec_signatures(target, source, env):
|
|
f = open(str(target[0]), 'w')
|
|
print >> f, '''
|
|
#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
|
|
#define __CPU_STATIC_INST_EXEC_SIGS_HH__
|
|
'''
|
|
for cpu in temp_cpu_list:
|
|
xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
|
|
print >> f, exec_sig_template % { 'type' : xc_type }
|
|
print >> f, '''
|
|
#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
|
|
'''
|
|
|
|
# Generate string that gets printed when header is rebuilt
|
|
def gen_sigs_string(target, source, env):
|
|
return " [GENERATE] static_inst_exec_sigs.hh: " \
|
|
+ ', '.join(temp_cpu_list)
|
|
|
|
# Add command to generate header to environment.
|
|
env.Command('static_inst_exec_sigs.hh', (),
|
|
Action(gen_cpu_exec_signatures, gen_sigs_string,
|
|
varlist = temp_cpu_list))
|
|
|
|
env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
|
|
env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
|
|
|
|
# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True
|
|
# and one of these are not being used.
|
|
CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
|
|
|
|
SimObject('BaseCPU.py')
|
|
SimObject('FuncUnit.py')
|
|
SimObject('ExeTracer.py')
|
|
SimObject('IntelTrace.py')
|
|
SimObject('NativeTrace.py')
|
|
|
|
Source('activity.cc')
|
|
Source('base.cc')
|
|
Source('cpuevent.cc')
|
|
Source('decode.cc')
|
|
Source('exetrace.cc')
|
|
Source('func_unit.cc')
|
|
Source('inteltrace.cc')
|
|
Source('nativetrace.cc')
|
|
Source('pc_event.cc')
|
|
Source('quiesce_event.cc')
|
|
Source('static_inst.cc')
|
|
Source('simple_thread.cc')
|
|
Source('thread_context.cc')
|
|
Source('thread_state.cc')
|
|
|
|
if env['FULL_SYSTEM']:
|
|
SimObject('IntrControl.py')
|
|
|
|
Source('intr_control.cc')
|
|
Source('profile.cc')
|
|
|
|
if env['TARGET_ISA'] == 'sparc':
|
|
SimObject('LegionTrace.py')
|
|
Source('legiontrace.cc')
|
|
|
|
if env['USE_CHECKER']:
|
|
Source('checker/cpu.cc')
|
|
DebugFlag('Checker')
|
|
checker_supports = False
|
|
for i in CheckerSupportedCPUList:
|
|
if i in env['CPU_MODELS']:
|
|
checker_supports = True
|
|
if not checker_supports:
|
|
print "Checker only supports CPU models",
|
|
for i in CheckerSupportedCPUList:
|
|
print i,
|
|
print ", please set USE_CHECKER=False or use one of those CPU models"
|
|
Exit(1)
|
|
|
|
DebugFlag('Activity')
|
|
DebugFlag('Commit')
|
|
DebugFlag('Context')
|
|
DebugFlag('Decode')
|
|
DebugFlag('DynInst')
|
|
DebugFlag('ExecEnable')
|
|
DebugFlag('ExecCPSeq')
|
|
DebugFlag('ExecEffAddr')
|
|
DebugFlag('ExecFaulting', 'Trace faulting instructions')
|
|
DebugFlag('ExecFetchSeq')
|
|
DebugFlag('ExecOpClass')
|
|
DebugFlag('ExecRegDelta')
|
|
DebugFlag('ExecResult')
|
|
DebugFlag('ExecSpeculative')
|
|
DebugFlag('ExecSymbol')
|
|
DebugFlag('ExecThread')
|
|
DebugFlag('ExecTicks')
|
|
DebugFlag('ExecMicro')
|
|
DebugFlag('ExecMacro')
|
|
DebugFlag('ExecUser')
|
|
DebugFlag('ExecKernel')
|
|
DebugFlag('ExecAsid')
|
|
DebugFlag('Fetch')
|
|
DebugFlag('IntrControl')
|
|
DebugFlag('O3PipeView')
|
|
DebugFlag('PCEvent')
|
|
DebugFlag('Quiesce')
|
|
|
|
CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
|
|
'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
|
|
'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
|
|
'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
|
|
'ExecAsid' ])
|
|
CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
|
|
'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
|
|
'ExecUser', 'ExecKernel' ])
|
|
CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
|
|
'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
|
|
'ExecUser', 'ExecKernel' ])
|