228 lines
6.5 KiB
C++
228 lines
6.5 KiB
C++
/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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#include "dev/pci/host.hh"
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#include <utility>
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#include "debug/PciHost.hh"
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#include "dev/pci/device.hh"
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#include "dev/platform.hh"
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#include "params/GenericPciHost.hh"
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#include "params/PciHost.hh"
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PciHost::PciHost(const PciHostParams *p)
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: PioDevice(p)
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{
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}
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PciHost::~PciHost()
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{
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}
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PciHost::DeviceInterface
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PciHost::registerDevice(PciDevice *device, PciBusAddr bus_addr, PciIntPin pin)
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{
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auto map_entry = devices.emplace(bus_addr, device);
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DPRINTF(PciHost, "%02x:%02x.%i: Registering device\n",
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bus_addr.bus, bus_addr.dev, bus_addr.func);
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fatal_if(!map_entry.second,
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"%02x:%02x.%i: PCI bus ID collision\n",
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bus_addr.bus, bus_addr.dev, bus_addr.func);
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return DeviceInterface(*this, bus_addr, pin);
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}
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PciDevice *
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PciHost::getDevice(const PciBusAddr &addr)
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{
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auto device = devices.find(addr);
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return device != devices.end() ? device->second : nullptr;
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}
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const PciDevice *
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PciHost::getDevice(const PciBusAddr &addr) const
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{
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auto device = devices.find(addr);
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return device != devices.end() ? device->second : nullptr;
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}
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PciHost::DeviceInterface::DeviceInterface(
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PciHost &_host,
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PciBusAddr &bus_addr, PciIntPin interrupt_pin)
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: host(_host),
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busAddr(bus_addr), interruptPin(interrupt_pin)
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{
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}
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const std::string
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PciHost::DeviceInterface::name() const
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{
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return csprintf("%s.interface[%02x:%02x.%i]",
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host.name(), busAddr.bus, busAddr.dev, busAddr.func);
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}
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void
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PciHost::DeviceInterface::postInt()
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{
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DPRINTF(PciHost, "postInt\n");
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host.postInt(busAddr, interruptPin);
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}
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void
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PciHost::DeviceInterface::clearInt()
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{
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DPRINTF(PciHost, "clearInt\n");
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host.clearInt(busAddr, interruptPin);
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}
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GenericPciHost::GenericPciHost(const GenericPciHostParams *p)
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: PciHost(p),
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platform(*p->platform),
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confBase(p->conf_base), confSize(p->conf_size),
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confDeviceBits(p->conf_device_bits),
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pciPioBase(p->pci_pio_base), pciMemBase(p->pci_mem_base),
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pciDmaBase(p->pci_dma_base)
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{
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}
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GenericPciHost::~GenericPciHost()
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{
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}
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Tick
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GenericPciHost::read(PacketPtr pkt)
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{
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const auto dev_addr(decodeAddress(pkt->getAddr() - confBase));
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const Addr size(pkt->getSize());
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DPRINTF(PciHost, "%02x:%02x.%i: read: offset=0x%x, size=0x%x\n",
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dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func,
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dev_addr.second,
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size);
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PciDevice *const pci_dev(getDevice(dev_addr.first));
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if (pci_dev) {
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// @todo Remove this after testing
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pkt->headerDelay = pkt->payloadDelay = 0;
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return pci_dev->readConfig(pkt);
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} else {
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uint8_t *pkt_data(pkt->getPtr<uint8_t>());
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std::fill(pkt_data, pkt_data + size, 0xFF);
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pkt->makeAtomicResponse();
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return 0;
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}
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}
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Tick
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GenericPciHost::write(PacketPtr pkt)
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{
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const auto dev_addr(decodeAddress(pkt->getAddr() - confBase));
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DPRINTF(PciHost, "%02x:%02x.%i: write: offset=0x%x, size=0x%x\n",
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dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func,
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dev_addr.second,
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pkt->getSize());
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PciDevice *const pci_dev(getDevice(dev_addr.first));
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panic_if(!pci_dev,
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"%02x:%02x.%i: Write to config space on non-existent PCI device\n",
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dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func);
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// @todo Remove this after testing
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pkt->headerDelay = pkt->payloadDelay = 0;
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return pci_dev->writeConfig(pkt);
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}
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AddrRangeList
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GenericPciHost::getAddrRanges() const
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{
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return AddrRangeList({ RangeSize(confBase, confSize) });
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}
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std::pair<PciBusAddr, Addr>
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GenericPciHost::decodeAddress(Addr addr)
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{
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const Addr offset(addr & mask(confDeviceBits));
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const Addr bus_addr(addr >> confDeviceBits);
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return std::make_pair(
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PciBusAddr(bits(bus_addr, 15, 8),
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bits(bus_addr, 7, 3),
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bits(bus_addr, 2, 0)),
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offset);
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}
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void
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GenericPciHost::postInt(const PciBusAddr &addr, PciIntPin pin)
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{
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platform.postPciInt(mapPciInterrupt(addr, pin));
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}
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void
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GenericPciHost::clearInt(const PciBusAddr &addr, PciIntPin pin)
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{
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platform.clearPciInt(mapPciInterrupt(addr, pin));
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}
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uint32_t
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GenericPciHost::mapPciInterrupt(const PciBusAddr &addr, PciIntPin pin) const
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{
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const PciDevice *dev(getDevice(addr));
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assert(dev);
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return dev->interruptLine();
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}
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GenericPciHost *
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GenericPciHostParams::create()
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{
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return new GenericPciHost(this);
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}
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