136 lines
4.4 KiB
C++
136 lines
4.4 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef __CPU_INORDER_TLB_UNIT_HH__
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#define __CPU_INORDER_TLB_UNIT_HH__
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#include <vector>
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#include <list>
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#include <string>
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#include "config/the_isa.hh"
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#include "cpu/inorder/resources/inst_buffer.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/cpu.hh"
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class TLBUnit : public Resource
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{
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public:
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typedef ThePipeline::DynInstPtr DynInstPtr;
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enum TLBCommand {
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FetchLookup,
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DataReadLookup,
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DataWriteLookup
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};
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public:
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TLBUnit(std::string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
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virtual ~TLBUnit() {}
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void init();
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int getSlot(DynInstPtr inst);
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virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
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int res_idx, int slot_num,
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unsigned cmd);
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virtual void execute(int slot_num);
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void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
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ThreadID tid);
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bool tlbBlocked[ThePipeline::MaxThreads];
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TheISA::TLB* tlb();
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protected:
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/** List of instructions this resource is currently
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* processing.
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*/
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std::list<DynInstPtr> instList;
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TheISA::TLB *_tlb;
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};
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class TLBUnitEvent : public ResourceEvent {
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public:
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/** Constructs a resource event. */
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TLBUnitEvent();
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virtual ~TLBUnitEvent() {}
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/** Processes a resource event. */
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virtual void process();
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};
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class TLBUnitRequest : public ResourceRequest {
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public:
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typedef ThePipeline::DynInstPtr DynInstPtr;
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public:
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TLBUnitRequest(TLBUnit *res, DynInstPtr inst, int stage_num, int res_idx, int slot_num,
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unsigned _cmd)
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: ResourceRequest(res, inst, stage_num, res_idx, slot_num, _cmd)
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{
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Addr aligned_addr;
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int req_size;
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unsigned flags;
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if (_cmd == TLBUnit::FetchLookup) {
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aligned_addr = inst->getMemAddr();
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req_size = sizeof(TheISA::MachInst);
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flags = 0;
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inst->fetchMemReq = new Request(inst->readTid(), aligned_addr, req_size,
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flags, inst->readPC(), res->cpu->readCpuId(), inst->readTid());
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memReq = inst->fetchMemReq;
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} else {
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aligned_addr = inst->getMemAddr();;
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req_size = 0; //inst->getMemAccSize();
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flags = 0; //inst->getMemFlags();
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if (req_size == 0 && (inst->isDataPrefetch() || inst->isInstPrefetch())) {
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req_size = 8;
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}
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inst->dataMemReq = new Request(inst->readTid(), aligned_addr, req_size,
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flags, inst->readPC(), res->cpu->readCpuId(), inst->readTid());
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memReq = inst->dataMemReq;
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}
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}
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RequestPtr memReq;
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};
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#endif //__CPU_INORDER_TLB_UNIT_HH__
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