121 lines
3.9 KiB
C++
121 lines
3.9 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef __CPU_INORDER_FETCH_SEQ_UNIT_HH__
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#define __CPU_INORDER_FETCH_SEQ_UNIT_HH__
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#include <vector>
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#include <list>
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#include <string>
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#include "config/the_isa.hh"
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#include "cpu/inorder/resource.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/cpu.hh"
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class FetchSeqUnit : public Resource {
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public:
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typedef ThePipeline::DynInstPtr DynInstPtr;
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enum Command {
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AssignNextPC,
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UpdateTargetPC
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};
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public:
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FetchSeqUnit(std::string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
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virtual ~FetchSeqUnit();
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virtual void init();
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virtual void activateThread(ThreadID tid);
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virtual void deactivateThread(ThreadID tid);
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virtual void suspendThread(ThreadID tid);
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virtual void execute(int slot_num);
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void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
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/** Override default Resource squash sequence. This actually,
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* looks in the global communication buffer to get squash
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* info
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*/
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virtual void squash(DynInstPtr inst, int squash_stage,
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InstSeqNum squash_seq_num, ThreadID tid);
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inline void squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid);
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protected:
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unsigned instSize;
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bool pcValid[ThePipeline::MaxThreads];
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int pcBlockStage[ThePipeline::MaxThreads];
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TheISA::IntReg PC[ThePipeline::MaxThreads];
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TheISA::IntReg nextPC[ThePipeline::MaxThreads];
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TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
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/** Tracks delay slot information for threads in ISAs which use
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* delay slots;
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*/
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struct DelaySlotInfo {
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InstSeqNum delaySlotSeqNum;
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InstSeqNum branchSeqNum;
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int numInsts;
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Addr targetAddr;
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bool targetReady;
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};
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DelaySlotInfo delaySlotInfo[ThePipeline::MaxThreads];
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/** Squash Seq. Nums*/
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InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
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/** Squash Seq. Nums*/
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Tick lastSquashCycle[ThePipeline::MaxThreads];
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/** @todo: Add Resource Stats Here */
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public:
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class FetchSeqEvent : public ResourceEvent {
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public:
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/** Constructs a resource event. */
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FetchSeqEvent();
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virtual ~FetchSeqEvent() {}
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/** Processes a resource event. */
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virtual void process();
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};
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};
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#endif
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