3ef797623a
This patch adds an IOCache to the example bigLITTLE configuration. An IOCache is required for correct DMA transfers when we have caches in the system. Change-Id: Ifeddc1b360aacbb16b1393f361dd98873c834012 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
272 lines
9.2 KiB
Python
272 lines
9.2 KiB
Python
# Copyright (c) 2016 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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# Gabor Dozsa
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# System components used by the bigLITTLE.py configuration script
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import m5
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from m5.objects import *
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m5.util.addToPath('../../')
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from common.Caches import *
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from common import CpuConfig
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class L1I(L1_ICache):
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tag_latency = 1
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data_latency = 1
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response_latency = 1
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mshrs = 4
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tgts_per_mshr = 8
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size = '48kB'
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assoc = 3
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class L1D(L1_DCache):
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tag_latency = 2
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data_latency = 2
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response_latency = 1
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mshrs = 16
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tgts_per_mshr = 16
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size = '32kB'
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assoc = 2
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write_buffers = 16
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class WalkCache(PageTableWalkerCache):
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tag_latency = 4
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data_latency = 4
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response_latency = 4
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mshrs = 6
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tgts_per_mshr = 8
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size = '1kB'
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assoc = 8
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write_buffers = 16
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class L2(L2Cache):
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tag_latency = 12
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data_latency = 12
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response_latency = 5
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mshrs = 32
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tgts_per_mshr = 8
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size = '1MB'
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assoc = 16
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write_buffers = 8
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clusivity='mostly_excl'
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class L3(Cache):
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size = '16MB'
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assoc = 16
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tag_latency = 20
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data_latency = 20
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response_latency = 20
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mshrs = 20
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tgts_per_mshr = 12
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clusivity='mostly_excl'
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class MemBus(SystemXBar):
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badaddr_responder = BadAddr(warn_access="warn")
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default = Self.badaddr_responder.pio
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class CpuCluster(SubSystem):
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def __init__(self, system, num_cpus, cpu_clock, cpu_voltage,
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cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
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super(CpuCluster, self).__init__()
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self._cpu_type = cpu_type
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self._l1i_type = l1i_type
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self._l1d_type = l1d_type
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self._wcache_type = wcache_type
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self._l2_type = l2_type
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assert num_cpus > 0
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self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
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self.clk_domain = SrcClockDomain(clock=cpu_clock,
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voltage_domain=self.voltage_domain)
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self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
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clk_domain=self.clk_domain)
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for idx in range(num_cpus) ]
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for cpu in self.cpus:
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cpu.createThreads()
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cpu.createInterruptController()
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cpu.socket_id = system.numCpuClusters()
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system.addCpuCluster(self, num_cpus)
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def requireCaches(self):
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return self._cpu_type.require_caches()
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def memoryMode(self):
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return self._cpu_type.memory_mode()
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def addL1(self):
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for cpu in self.cpus:
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l1i = None if self._l1i_type is None else self._l1i_type()
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l1d = None if self._l1d_type is None else self._l1d_type()
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iwc = None if self._wcache_type is None else self._wcache_type()
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dwc = None if self._wcache_type is None else self._wcache_type()
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cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
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def addL2(self, clk_domain):
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if self._l2_type is None:
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return
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self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
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self.l2 = self._l2_type()
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for cpu in self.cpus:
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cpu.connectAllPorts(self.toL2Bus)
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self.toL2Bus.master = self.l2.cpu_side
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def connectMemSide(self, bus):
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bus.slave
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try:
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self.l2.mem_side = bus.slave
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except AttributeError:
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for cpu in self.cpus:
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cpu.connectAllPorts(bus)
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class AtomicCluster(CpuCluster):
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def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
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cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ]
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super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
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cpu_voltage, *cpu_config)
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def addL1(self):
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pass
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class SimpleSystem(LinuxArmSystem):
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cache_line_size = 64
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def __init__(self, caches, mem_size, **kwargs):
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super(SimpleSystem, self).__init__(**kwargs)
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self.voltage_domain = VoltageDomain(voltage="1.0V")
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self.clk_domain = SrcClockDomain(clock="1GHz",
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voltage_domain=Parent.voltage_domain)
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self.realview = VExpress_GEM5_V1()
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.flags_addr = self.realview.realview_io.pio_addr + 0x30
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self.membus = MemBus()
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.vncserver = VncServer()
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self.iobus = IOXBar()
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# CPUs->PIO
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self.iobridge = Bridge(delay='50ns')
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# Device DMA -> MEM
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mem_range = self.realview._mem_regions[0]
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mem_range_size = long(mem_range[1]) - long(mem_range[0])
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assert mem_range_size >= long(Addr(mem_size))
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self._mem_range = AddrRange(start=mem_range[0], size=mem_size)
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self._caches = caches
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if self._caches:
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self.iocache = IOCache(addr_ranges=[self._mem_range])
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else:
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self.dmabridge = Bridge(delay='50ns',
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ranges=[self._mem_range])
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self._pci_devices = 0
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self._clusters = []
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self._num_cpus = 0
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def attach_pci(self, dev):
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dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
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self._pci_devices += 1
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self.realview.attachPciDevice(dev, self.iobus)
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def connect(self):
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self.iobridge.master = self.iobus.slave
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self.iobridge.slave = self.membus.master
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if self._caches:
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self.iocache.mem_side = self.membus.slave
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self.iocache.cpu_side = self.iobus.master
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else:
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self.dmabridge.master = self.membus.slave
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self.dmabridge.slave = self.iobus.master
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.realview.attachOnChipIO(self.membus, self.iobridge)
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self.realview.attachIO(self.iobus)
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self.system_port = self.membus.slave
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def numCpuClusters(self):
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return len(self._clusters)
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def addCpuCluster(self, cpu_cluster, num_cpus):
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assert cpu_cluster not in self._clusters
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assert num_cpus > 0
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self._clusters.append(cpu_cluster)
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self._num_cpus += num_cpus
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def numCpus(self):
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return self._num_cpus
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def addCaches(self, need_caches, last_cache_level):
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if not need_caches:
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# connect each cluster to the memory hierarchy
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for cluster in self._clusters:
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cluster.connectMemSide(self.membus)
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return
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cluster_mem_bus = self.membus
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assert last_cache_level >= 1 and last_cache_level <= 3
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for cluster in self._clusters:
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cluster.addL1()
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if last_cache_level > 1:
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for cluster in self._clusters:
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cluster.addL2(cluster.clk_domain)
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if last_cache_level > 2:
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max_clock_cluster = max(self._clusters,
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key=lambda c: c.clk_domain.clock[0])
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self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
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self.toL3Bus = L2XBar(width=64)
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self.toL3Bus.master = self.l3.cpu_side
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self.l3.mem_side = self.membus.slave
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cluster_mem_bus = self.toL3Bus
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# connect each cluster to the memory hierarchy
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for cluster in self._clusters:
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cluster.connectMemSide(cluster_mem_bus)
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