gem5/src
Anthony Gutierrez a628afedad mem: refactor LRU cache tags and add random replacement tags
this patch implements a new tags class that uses a random replacement policy.
these tags prefer to evict invalid blocks first, if none are available a
replacement candidate is chosen at random.

this patch factors out the common code in the LRU class and creates a new
abstract class: the BaseSetAssoc class. any set associative tag class must
implement the functionality related to the actual replacement policy in the
following methods:

accessBlock()
findVictim()
insertBlock()
invalidate()
2014-07-28 12:23:23 -04:00
..
arch power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
base cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
cpu cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
dev x86: make PioBus return BadAddress errors 2014-07-18 22:05:51 -07:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern kern: get rid of unused linux syscall files 2014-07-18 22:05:51 -07:00
mem mem: refactor LRU cache tags and add random replacement tags 2014-07-28 12:23:23 -04:00
proto mem: Edit proto Packet and enhance the python script 2014-03-07 15:56:23 -05:00
python cpu: Add flag name printing to StaticInst 2014-05-09 18:58:47 -04:00
sim cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
unittest unittest: Fix build errors 2014-01-30 12:21:58 -06:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript scons: Bump the compiler version to gcc 4.6 and clang 3.0 2014-06-10 17:44:39 -04:00