1226 lines
35 KiB
C++
1226 lines
35 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_INSTS_VFP_HH__
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#define __ARCH_ARM_INSTS_VFP_HH__
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#include "arch/arm/insts/misc.hh"
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#include "arch/arm/miscregs.hh"
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#include <fenv.h>
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#include <cmath>
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namespace ArmISA
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{
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enum VfpMicroMode {
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VfpNotAMicroop,
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VfpMicroop,
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VfpFirstMicroop,
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VfpLastMicroop
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};
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template<class T>
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static inline void
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setVfpMicroFlags(VfpMicroMode mode, T &flags)
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{
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switch (mode) {
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case VfpMicroop:
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flags[StaticInst::IsMicroop] = true;
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break;
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case VfpFirstMicroop:
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flags[StaticInst::IsMicroop] =
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flags[StaticInst::IsFirstMicroop] = true;
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break;
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case VfpLastMicroop:
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flags[StaticInst::IsMicroop] =
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flags[StaticInst::IsLastMicroop] = true;
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break;
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case VfpNotAMicroop:
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break;
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}
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if (mode == VfpMicroop || mode == VfpFirstMicroop) {
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flags[StaticInst::IsDelayedCommit] = true;
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}
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}
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enum FeExceptionBit
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{
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FeDivByZero = FE_DIVBYZERO,
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FeInexact = FE_INEXACT,
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FeInvalid = FE_INVALID,
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FeOverflow = FE_OVERFLOW,
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FeUnderflow = FE_UNDERFLOW,
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FeAllExceptions = FE_ALL_EXCEPT
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};
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enum FeRoundingMode
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{
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FeRoundDown = FE_DOWNWARD,
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FeRoundNearest = FE_TONEAREST,
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FeRoundZero = FE_TOWARDZERO,
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FeRoundUpward = FE_UPWARD
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};
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enum VfpRoundingMode
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{
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VfpRoundNearest = 0,
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VfpRoundUpward = 1,
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VfpRoundDown = 2,
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VfpRoundZero = 3
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};
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template <class fpType>
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static inline bool
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flushToZero(fpType &op)
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{
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fpType junk = 0.0;
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if (std::fpclassify(op) == FP_SUBNORMAL) {
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uint64_t bitMask = ULL(0x1) << (sizeof(fpType) * 8 - 1);
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op = bitsToFp(fpToBits(op) & bitMask, junk);
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return true;
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}
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return false;
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}
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template <class fpType>
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static inline bool
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flushToZero(fpType &op1, fpType &op2)
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{
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bool flush1 = flushToZero(op1);
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bool flush2 = flushToZero(op2);
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return flush1 || flush2;
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}
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template <class fpType>
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static inline void
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vfpFlushToZero(FPSCR &fpscr, fpType &op)
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{
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if (fpscr.fz == 1 && flushToZero(op)) {
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fpscr.idc = 1;
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}
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}
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template <class fpType>
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static inline void
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vfpFlushToZero(FPSCR &fpscr, fpType &op1, fpType &op2)
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{
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vfpFlushToZero(fpscr, op1);
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vfpFlushToZero(fpscr, op2);
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}
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static inline uint32_t
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fpToBits(float fp)
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{
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union
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{
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float fp;
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uint32_t bits;
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} val;
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val.fp = fp;
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return val.bits;
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}
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static inline uint64_t
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fpToBits(double fp)
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{
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union
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{
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double fp;
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uint64_t bits;
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} val;
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val.fp = fp;
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return val.bits;
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}
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static inline float
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bitsToFp(uint64_t bits, float junk)
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{
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union
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{
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float fp;
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uint32_t bits;
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} val;
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val.bits = bits;
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return val.fp;
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}
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static inline double
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bitsToFp(uint64_t bits, double junk)
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{
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union
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{
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double fp;
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uint64_t bits;
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} val;
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val.bits = bits;
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return val.fp;
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}
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typedef int VfpSavedState;
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static inline VfpSavedState
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prepFpState(uint32_t rMode)
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{
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int roundingMode = fegetround();
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feclearexcept(FeAllExceptions);
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switch (rMode) {
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case VfpRoundNearest:
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fesetround(FeRoundNearest);
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break;
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case VfpRoundUpward:
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fesetround(FeRoundUpward);
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break;
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case VfpRoundDown:
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fesetround(FeRoundDown);
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break;
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case VfpRoundZero:
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fesetround(FeRoundZero);
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break;
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}
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return roundingMode;
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}
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static inline void
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finishVfp(FPSCR &fpscr, VfpSavedState state)
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{
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int exceptions = fetestexcept(FeAllExceptions);
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bool underflow = false;
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if (exceptions & FeInvalid) {
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fpscr.ioc = 1;
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}
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if (exceptions & FeDivByZero) {
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fpscr.dzc = 1;
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}
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if (exceptions & FeOverflow) {
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fpscr.ofc = 1;
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}
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if (exceptions & FeUnderflow) {
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underflow = true;
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fpscr.ufc = 1;
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}
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if ((exceptions & FeInexact) && !(underflow && fpscr.fz)) {
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fpscr.ixc = 1;
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}
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fesetround(state);
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}
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template <class fpType>
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static inline fpType
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fixDest(FPSCR fpscr, fpType val, fpType op1)
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{
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int fpClass = std::fpclassify(val);
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fpType junk = 0.0;
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if (fpClass == FP_NAN) {
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const bool single = (sizeof(val) == sizeof(float));
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const uint64_t qnan = single ? 0x7fc00000 : ULL(0x7ff8000000000000);
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const bool nan = std::isnan(op1);
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if (!nan || (fpscr.dn == 1)) {
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val = bitsToFp(qnan, junk);
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} else if (nan) {
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val = bitsToFp(fpToBits(op1) | qnan, junk);
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}
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} else if (fpClass == FP_SUBNORMAL && fpscr.fz == 1) {
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// Turn val into a zero with the correct sign;
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uint64_t bitMask = ULL(0x1) << (sizeof(fpType) * 8 - 1);
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val = bitsToFp(fpToBits(val) & bitMask, junk);
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feclearexcept(FeInexact);
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feraiseexcept(FeUnderflow);
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}
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return val;
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}
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template <class fpType>
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static inline fpType
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fixDest(FPSCR fpscr, fpType val, fpType op1, fpType op2)
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{
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int fpClass = std::fpclassify(val);
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fpType junk = 0.0;
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if (fpClass == FP_NAN) {
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const bool single = (sizeof(val) == sizeof(float));
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const uint64_t qnan = single ? 0x7fc00000 : ULL(0x7ff8000000000000);
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const bool nan1 = std::isnan(op1);
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const bool nan2 = std::isnan(op2);
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const bool signal1 = nan1 && ((fpToBits(op1) & qnan) != qnan);
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const bool signal2 = nan2 && ((fpToBits(op2) & qnan) != qnan);
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if ((!nan1 && !nan2) || (fpscr.dn == 1)) {
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val = bitsToFp(qnan, junk);
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} else if (signal1) {
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val = bitsToFp(fpToBits(op1) | qnan, junk);
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} else if (signal2) {
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val = bitsToFp(fpToBits(op2) | qnan, junk);
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} else if (nan1) {
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val = op1;
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} else if (nan2) {
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val = op2;
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}
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} else if (fpClass == FP_SUBNORMAL && fpscr.fz == 1) {
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// Turn val into a zero with the correct sign;
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uint64_t bitMask = ULL(0x1) << (sizeof(fpType) * 8 - 1);
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val = bitsToFp(fpToBits(val) & bitMask, junk);
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feclearexcept(FeInexact);
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feraiseexcept(FeUnderflow);
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}
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return val;
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}
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template <class fpType>
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static inline fpType
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fixDivDest(FPSCR fpscr, fpType val, fpType op1, fpType op2)
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{
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fpType mid = fixDest(fpscr, val, op1, op2);
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const bool single = (sizeof(fpType) == sizeof(float));
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const fpType junk = 0.0;
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if ((single && (val == bitsToFp(0x00800000, junk) ||
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val == bitsToFp(0x80800000, junk))) ||
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(!single && (val == bitsToFp(ULL(0x0010000000000000), junk) ||
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val == bitsToFp(ULL(0x8010000000000000), junk)))
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) {
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__asm__ __volatile__("" : "=m" (op1) : "m" (op1));
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fesetround(FeRoundZero);
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fpType temp = 0.0;
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__asm__ __volatile__("" : "=m" (temp) : "m" (temp));
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temp = op1 / op2;
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if (flushToZero(temp)) {
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feraiseexcept(FeUnderflow);
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if (fpscr.fz) {
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feclearexcept(FeInexact);
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mid = temp;
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}
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}
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__asm__ __volatile__("" :: "m" (temp));
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}
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return mid;
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}
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static inline float
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fixFpDFpSDest(FPSCR fpscr, double val)
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{
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const float junk = 0.0;
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float op1 = 0.0;
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if (std::isnan(val)) {
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uint64_t valBits = fpToBits(val);
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uint32_t op1Bits = bits(valBits, 50, 29) |
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(mask(9) << 22) |
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(bits(valBits, 63) << 31);
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op1 = bitsToFp(op1Bits, junk);
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}
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float mid = fixDest(fpscr, (float)val, op1);
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if (fpscr.fz && fetestexcept(FeUnderflow | FeInexact) ==
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(FeUnderflow | FeInexact)) {
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feclearexcept(FeInexact);
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}
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if (mid == bitsToFp(0x00800000, junk) ||
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mid == bitsToFp(0x80800000, junk)) {
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__asm__ __volatile__("" : "=m" (val) : "m" (val));
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fesetround(FeRoundZero);
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float temp = 0.0;
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__asm__ __volatile__("" : "=m" (temp) : "m" (temp));
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temp = val;
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if (flushToZero(temp)) {
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feraiseexcept(FeUnderflow);
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if (fpscr.fz) {
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feclearexcept(FeInexact);
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mid = temp;
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}
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}
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__asm__ __volatile__("" :: "m" (temp));
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}
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return mid;
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}
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static inline double
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fixFpSFpDDest(FPSCR fpscr, float val)
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{
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const double junk = 0.0;
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double op1 = 0.0;
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if (std::isnan(val)) {
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uint32_t valBits = fpToBits(val);
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uint64_t op1Bits = ((uint64_t)bits(valBits, 21, 0) << 29) |
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(mask(12) << 51) |
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((uint64_t)bits(valBits, 31) << 63);
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op1 = bitsToFp(op1Bits, junk);
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}
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double mid = fixDest(fpscr, (double)val, op1);
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if (mid == bitsToFp(ULL(0x0010000000000000), junk) ||
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mid == bitsToFp(ULL(0x8010000000000000), junk)) {
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__asm__ __volatile__("" : "=m" (val) : "m" (val));
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fesetround(FeRoundZero);
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double temp = 0.0;
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__asm__ __volatile__("" : "=m" (temp) : "m" (temp));
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temp = val;
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if (flushToZero(temp)) {
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feraiseexcept(FeUnderflow);
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if (fpscr.fz) {
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feclearexcept(FeInexact);
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mid = temp;
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}
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}
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__asm__ __volatile__("" :: "m" (temp));
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}
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return mid;
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}
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static inline float
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vcvtFpSFpH(FPSCR &fpscr, float op, float dest, bool top)
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{
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float junk = 0.0;
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uint32_t destBits = fpToBits(dest);
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uint32_t opBits = fpToBits(op);
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// Extract the operand.
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bool neg = bits(opBits, 31);
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uint32_t exponent = bits(opBits, 30, 23);
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uint32_t oldMantissa = bits(opBits, 22, 0);
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uint32_t mantissa = oldMantissa >> (23 - 10);
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// Do the conversion.
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uint32_t extra = oldMantissa & mask(23 - 10);
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if (exponent == 0xff) {
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if (oldMantissa != 0) {
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// Nans.
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if (bits(mantissa, 9) == 0) {
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// Signalling nan.
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fpscr.ioc = 1;
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}
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if (fpscr.ahp) {
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mantissa = 0;
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exponent = 0;
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fpscr.ioc = 1;
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} else if (fpscr.dn) {
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mantissa = (1 << 9);
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exponent = 0x1f;
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neg = false;
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} else {
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exponent = 0x1f;
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mantissa |= (1 << 9);
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}
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} else {
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// Infinities.
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exponent = 0x1F;
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if (fpscr.ahp) {
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fpscr.ioc = 1;
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mantissa = 0x3ff;
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} else {
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mantissa = 0;
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}
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}
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} else if (exponent == 0 && oldMantissa == 0) {
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// Zero, don't need to do anything.
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} else {
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// Normalized or denormalized numbers.
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bool inexact = (extra != 0);
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|
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if (exponent == 0) {
|
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// Denormalized.
|
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// If flush to zero is on, this shouldn't happen.
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assert(fpscr.fz == 0);
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|
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// Check for underflow
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if (inexact || fpscr.ufe)
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fpscr.ufc = 1;
|
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|
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// Handle rounding.
|
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unsigned mode = fpscr.rMode;
|
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if ((mode == VfpRoundUpward && !neg && extra) ||
|
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(mode == VfpRoundDown && neg && extra) ||
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(mode == VfpRoundNearest &&
|
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(extra > (1 << 9) ||
|
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(extra == (1 << 9) && bits(mantissa, 0))))) {
|
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mantissa++;
|
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}
|
|
|
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// See if the number became normalized after rounding.
|
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if (mantissa == (1 << 10)) {
|
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mantissa = 0;
|
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exponent = 1;
|
|
}
|
|
} else {
|
|
// Normalized.
|
|
|
|
// We need to track the dropped bits differently since
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// more can be dropped by denormalizing.
|
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bool topOne = bits(extra, 12);
|
|
bool restZeros = bits(extra, 11, 0) == 0;
|
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|
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if (exponent <= (127 - 15)) {
|
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// The result is too small. Denormalize.
|
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mantissa |= (1 << 10);
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while (mantissa && exponent <= (127 - 15)) {
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restZeros = restZeros && !topOne;
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topOne = bits(mantissa, 0);
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mantissa = mantissa >> 1;
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exponent++;
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}
|
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if (topOne || !restZeros)
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inexact = true;
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exponent = 0;
|
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} else {
|
|
// Change bias.
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|
exponent -= (127 - 15);
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}
|
|
|
|
if (exponent == 0 && (inexact || fpscr.ufe)) {
|
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// Underflow
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fpscr.ufc = 1;
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}
|
|
|
|
// Handle rounding.
|
|
unsigned mode = fpscr.rMode;
|
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bool nonZero = topOne || !restZeros;
|
|
if ((mode == VfpRoundUpward && !neg && nonZero) ||
|
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(mode == VfpRoundDown && neg && nonZero) ||
|
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(mode == VfpRoundNearest && topOne &&
|
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(!restZeros || bits(mantissa, 0)))) {
|
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mantissa++;
|
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}
|
|
|
|
// See if we rounded up and need to bump the exponent.
|
|
if (mantissa == (1 << 10)) {
|
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mantissa = 0;
|
|
exponent++;
|
|
}
|
|
|
|
// Deal with overflow
|
|
if (fpscr.ahp) {
|
|
if (exponent >= 0x20) {
|
|
exponent = 0x1f;
|
|
mantissa = 0x3ff;
|
|
fpscr.ioc = 1;
|
|
// Supress inexact exception.
|
|
inexact = false;
|
|
}
|
|
} else {
|
|
if (exponent >= 0x1f) {
|
|
if ((mode == VfpRoundNearest) ||
|
|
(mode == VfpRoundUpward && !neg) ||
|
|
(mode == VfpRoundDown && neg)) {
|
|
// Overflow to infinity.
|
|
exponent = 0x1f;
|
|
mantissa = 0;
|
|
} else {
|
|
// Overflow to max normal.
|
|
exponent = 0x1e;
|
|
mantissa = 0x3ff;
|
|
}
|
|
fpscr.ofc = 1;
|
|
inexact = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (inexact) {
|
|
fpscr.ixc = 1;
|
|
}
|
|
}
|
|
// Reassemble and install the result.
|
|
uint32_t result = bits(mantissa, 9, 0);
|
|
replaceBits(result, 14, 10, exponent);
|
|
if (neg)
|
|
result |= (1 << 15);
|
|
if (top)
|
|
replaceBits(destBits, 31, 16, result);
|
|
else
|
|
replaceBits(destBits, 15, 0, result);
|
|
return bitsToFp(destBits, junk);
|
|
}
|
|
|
|
static inline float
|
|
vcvtFpHFpS(FPSCR &fpscr, float op, bool top)
|
|
{
|
|
float junk = 0.0;
|
|
uint32_t opBits = fpToBits(op);
|
|
// Extract the operand.
|
|
if (top)
|
|
opBits = bits(opBits, 31, 16);
|
|
else
|
|
opBits = bits(opBits, 15, 0);
|
|
// Extract the bitfields.
|
|
bool neg = bits(opBits, 15);
|
|
uint32_t exponent = bits(opBits, 14, 10);
|
|
uint32_t mantissa = bits(opBits, 9, 0);
|
|
// Do the conversion.
|
|
if (exponent == 0) {
|
|
if (mantissa != 0) {
|
|
// Normalize the value.
|
|
exponent = exponent + (127 - 15) + 1;
|
|
while (mantissa < (1 << 10)) {
|
|
mantissa = mantissa << 1;
|
|
exponent--;
|
|
}
|
|
}
|
|
mantissa = mantissa << (23 - 10);
|
|
} else if (exponent == 0x1f && !fpscr.ahp) {
|
|
// Infinities and nans.
|
|
exponent = 0xff;
|
|
if (mantissa != 0) {
|
|
// Nans.
|
|
mantissa = mantissa << (23 - 10);
|
|
if (bits(mantissa, 22) == 0) {
|
|
// Signalling nan.
|
|
fpscr.ioc = 1;
|
|
mantissa |= (1 << 22);
|
|
}
|
|
if (fpscr.dn) {
|
|
mantissa &= ~mask(22);
|
|
neg = false;
|
|
}
|
|
}
|
|
} else {
|
|
exponent = exponent + (127 - 15);
|
|
mantissa = mantissa << (23 - 10);
|
|
}
|
|
// Reassemble the result.
|
|
uint32_t result = bits(mantissa, 22, 0);
|
|
replaceBits(result, 30, 23, exponent);
|
|
if (neg)
|
|
result |= (1 << 31);
|
|
return bitsToFp(result, junk);
|
|
}
|
|
|
|
static inline double
|
|
makeDouble(uint32_t low, uint32_t high)
|
|
{
|
|
double junk = 0.0;
|
|
return bitsToFp((uint64_t)low | ((uint64_t)high << 32), junk);
|
|
}
|
|
|
|
static inline uint32_t
|
|
lowFromDouble(double val)
|
|
{
|
|
return fpToBits(val);
|
|
}
|
|
|
|
static inline uint32_t
|
|
highFromDouble(double val)
|
|
{
|
|
return fpToBits(val) >> 32;
|
|
}
|
|
|
|
static inline uint64_t
|
|
vfpFpSToFixed(float val, bool isSigned, bool half,
|
|
uint8_t imm, bool rzero = true)
|
|
{
|
|
int rmode = rzero ? FeRoundZero : fegetround();
|
|
__asm__ __volatile__("" : "=m" (rmode) : "m" (rmode));
|
|
fesetround(FeRoundNearest);
|
|
val = val * powf(2.0, imm);
|
|
__asm__ __volatile__("" : "=m" (val) : "m" (val));
|
|
fesetround(rmode);
|
|
feclearexcept(FeAllExceptions);
|
|
__asm__ __volatile__("" : "=m" (val) : "m" (val));
|
|
float origVal = val;
|
|
val = rintf(val);
|
|
int fpType = std::fpclassify(val);
|
|
if (fpType == FP_SUBNORMAL || fpType == FP_NAN) {
|
|
if (fpType == FP_NAN) {
|
|
feraiseexcept(FeInvalid);
|
|
}
|
|
val = 0.0;
|
|
} else if (origVal != val) {
|
|
switch (rmode) {
|
|
case FeRoundNearest:
|
|
if (origVal - val > 0.5)
|
|
val += 1.0;
|
|
else if (val - origVal > 0.5)
|
|
val -= 1.0;
|
|
break;
|
|
case FeRoundDown:
|
|
if (origVal < val)
|
|
val -= 1.0;
|
|
break;
|
|
case FeRoundUpward:
|
|
if (origVal > val)
|
|
val += 1.0;
|
|
break;
|
|
}
|
|
feraiseexcept(FeInexact);
|
|
}
|
|
|
|
if (isSigned) {
|
|
if (half) {
|
|
if ((double)val < (int16_t)(1 << 15)) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return (int16_t)(1 << 15);
|
|
}
|
|
if ((double)val > (int16_t)mask(15)) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return (int16_t)mask(15);
|
|
}
|
|
return (int16_t)val;
|
|
} else {
|
|
if ((double)val < (int32_t)(1 << 31)) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return (int32_t)(1 << 31);
|
|
}
|
|
if ((double)val > (int32_t)mask(31)) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return (int32_t)mask(31);
|
|
}
|
|
return (int32_t)val;
|
|
}
|
|
} else {
|
|
if (half) {
|
|
if ((double)val < 0) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return 0;
|
|
}
|
|
if ((double)val > (mask(16))) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return mask(16);
|
|
}
|
|
return (uint16_t)val;
|
|
} else {
|
|
if ((double)val < 0) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return 0;
|
|
}
|
|
if ((double)val > (mask(32))) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return mask(32);
|
|
}
|
|
return (uint32_t)val;
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline float
|
|
vfpUFixedToFpS(FPSCR fpscr, uint32_t val, bool half, uint8_t imm)
|
|
{
|
|
fesetround(FeRoundNearest);
|
|
if (half)
|
|
val = (uint16_t)val;
|
|
float scale = powf(2.0, imm);
|
|
__asm__ __volatile__("" : "=m" (scale) : "m" (scale));
|
|
feclearexcept(FeAllExceptions);
|
|
__asm__ __volatile__("" : "=m" (scale) : "m" (scale));
|
|
return fixDivDest(fpscr, val / scale, (float)val, scale);
|
|
}
|
|
|
|
static inline float
|
|
vfpSFixedToFpS(FPSCR fpscr, int32_t val, bool half, uint8_t imm)
|
|
{
|
|
fesetround(FeRoundNearest);
|
|
if (half)
|
|
val = sext<16>(val & mask(16));
|
|
float scale = powf(2.0, imm);
|
|
__asm__ __volatile__("" : "=m" (scale) : "m" (scale));
|
|
feclearexcept(FeAllExceptions);
|
|
__asm__ __volatile__("" : "=m" (scale) : "m" (scale));
|
|
return fixDivDest(fpscr, val / scale, (float)val, scale);
|
|
}
|
|
|
|
static inline uint64_t
|
|
vfpFpDToFixed(double val, bool isSigned, bool half,
|
|
uint8_t imm, bool rzero = true)
|
|
{
|
|
int rmode = rzero ? FeRoundZero : fegetround();
|
|
fesetround(FeRoundNearest);
|
|
val = val * pow(2.0, imm);
|
|
__asm__ __volatile__("" : "=m" (val) : "m" (val));
|
|
fesetround(rmode);
|
|
feclearexcept(FeAllExceptions);
|
|
__asm__ __volatile__("" : "=m" (val) : "m" (val));
|
|
double origVal = val;
|
|
val = rint(val);
|
|
int fpType = std::fpclassify(val);
|
|
if (fpType == FP_SUBNORMAL || fpType == FP_NAN) {
|
|
if (fpType == FP_NAN) {
|
|
feraiseexcept(FeInvalid);
|
|
}
|
|
val = 0.0;
|
|
} else if (origVal != val) {
|
|
switch (rmode) {
|
|
case FeRoundNearest:
|
|
if (origVal - val > 0.5)
|
|
val += 1.0;
|
|
else if (val - origVal > 0.5)
|
|
val -= 1.0;
|
|
break;
|
|
case FeRoundDown:
|
|
if (origVal < val)
|
|
val -= 1.0;
|
|
break;
|
|
case FeRoundUpward:
|
|
if (origVal > val)
|
|
val += 1.0;
|
|
break;
|
|
}
|
|
feraiseexcept(FeInexact);
|
|
}
|
|
if (isSigned) {
|
|
if (half) {
|
|
if (val < (int16_t)(1 << 15)) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return (int16_t)(1 << 15);
|
|
}
|
|
if (val > (int16_t)mask(15)) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return (int16_t)mask(15);
|
|
}
|
|
return (int16_t)val;
|
|
} else {
|
|
if (val < (int32_t)(1 << 31)) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return (int32_t)(1 << 31);
|
|
}
|
|
if (val > (int32_t)mask(31)) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return (int32_t)mask(31);
|
|
}
|
|
return (int32_t)val;
|
|
}
|
|
} else {
|
|
if (half) {
|
|
if (val < 0) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return 0;
|
|
}
|
|
if (val > mask(16)) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return mask(16);
|
|
}
|
|
return (uint16_t)val;
|
|
} else {
|
|
if (val < 0) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return 0;
|
|
}
|
|
if (val > mask(32)) {
|
|
feraiseexcept(FeInvalid);
|
|
feclearexcept(FeInexact);
|
|
return mask(32);
|
|
}
|
|
return (uint32_t)val;
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline double
|
|
vfpUFixedToFpD(FPSCR fpscr, uint32_t val, bool half, uint8_t imm)
|
|
{
|
|
fesetround(FeRoundNearest);
|
|
if (half)
|
|
val = (uint16_t)val;
|
|
double scale = pow(2.0, imm);
|
|
__asm__ __volatile__("" : "=m" (scale) : "m" (scale));
|
|
feclearexcept(FeAllExceptions);
|
|
__asm__ __volatile__("" : "=m" (scale) : "m" (scale));
|
|
return fixDivDest(fpscr, val / scale, (double)val, scale);
|
|
}
|
|
|
|
static inline double
|
|
vfpSFixedToFpD(FPSCR fpscr, int32_t val, bool half, uint8_t imm)
|
|
{
|
|
fesetround(FeRoundNearest);
|
|
if (half)
|
|
val = sext<16>(val & mask(16));
|
|
double scale = pow(2.0, imm);
|
|
__asm__ __volatile__("" : "=m" (scale) : "m" (scale));
|
|
feclearexcept(FeAllExceptions);
|
|
__asm__ __volatile__("" : "=m" (scale) : "m" (scale));
|
|
return fixDivDest(fpscr, val / scale, (double)val, scale);
|
|
}
|
|
|
|
class VfpMacroOp : public PredMacroOp
|
|
{
|
|
public:
|
|
static bool
|
|
inScalarBank(IntRegIndex idx)
|
|
{
|
|
return (idx % 32) < 8;
|
|
}
|
|
|
|
protected:
|
|
bool wide;
|
|
|
|
VfpMacroOp(const char *mnem, ExtMachInst _machInst,
|
|
OpClass __opClass, bool _wide) :
|
|
PredMacroOp(mnem, _machInst, __opClass), wide(_wide)
|
|
{}
|
|
|
|
IntRegIndex
|
|
addStride(IntRegIndex idx, unsigned stride)
|
|
{
|
|
if (wide) {
|
|
stride *= 2;
|
|
}
|
|
unsigned offset = idx % 8;
|
|
idx = (IntRegIndex)(idx - offset);
|
|
offset += stride;
|
|
idx = (IntRegIndex)(idx + (offset % 8));
|
|
return idx;
|
|
}
|
|
|
|
void
|
|
nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2)
|
|
{
|
|
unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
|
|
assert(!inScalarBank(dest));
|
|
dest = addStride(dest, stride);
|
|
op1 = addStride(op1, stride);
|
|
if (!inScalarBank(op2)) {
|
|
op2 = addStride(op2, stride);
|
|
}
|
|
}
|
|
|
|
void
|
|
nextIdxs(IntRegIndex &dest, IntRegIndex &op1)
|
|
{
|
|
unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
|
|
assert(!inScalarBank(dest));
|
|
dest = addStride(dest, stride);
|
|
if (!inScalarBank(op1)) {
|
|
op1 = addStride(op1, stride);
|
|
}
|
|
}
|
|
|
|
void
|
|
nextIdxs(IntRegIndex &dest)
|
|
{
|
|
unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
|
|
assert(!inScalarBank(dest));
|
|
dest = addStride(dest, stride);
|
|
}
|
|
};
|
|
|
|
static inline float
|
|
fpAddS(float a, float b)
|
|
{
|
|
return a + b;
|
|
}
|
|
|
|
static inline double
|
|
fpAddD(double a, double b)
|
|
{
|
|
return a + b;
|
|
}
|
|
|
|
static inline float
|
|
fpSubS(float a, float b)
|
|
{
|
|
return a - b;
|
|
}
|
|
|
|
static inline double
|
|
fpSubD(double a, double b)
|
|
{
|
|
return a - b;
|
|
}
|
|
|
|
static inline float
|
|
fpDivS(float a, float b)
|
|
{
|
|
return a / b;
|
|
}
|
|
|
|
static inline double
|
|
fpDivD(double a, double b)
|
|
{
|
|
return a / b;
|
|
}
|
|
|
|
static inline float
|
|
fpMulS(float a, float b)
|
|
{
|
|
return a * b;
|
|
}
|
|
|
|
static inline double
|
|
fpMulD(double a, double b)
|
|
{
|
|
return a * b;
|
|
}
|
|
|
|
class FpOp : public PredOp
|
|
{
|
|
protected:
|
|
FpOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
|
|
PredOp(mnem, _machInst, __opClass)
|
|
{}
|
|
|
|
virtual float
|
|
doOp(float op1, float op2) const
|
|
{
|
|
panic("Unimplemented version of doOp called.\n");
|
|
}
|
|
|
|
virtual float
|
|
doOp(float op1) const
|
|
{
|
|
panic("Unimplemented version of doOp called.\n");
|
|
}
|
|
|
|
virtual double
|
|
doOp(double op1, double op2) const
|
|
{
|
|
panic("Unimplemented version of doOp called.\n");
|
|
}
|
|
|
|
virtual double
|
|
doOp(double op1) const
|
|
{
|
|
panic("Unimplemented version of doOp called.\n");
|
|
}
|
|
|
|
double
|
|
dbl(uint32_t low, uint32_t high) const
|
|
{
|
|
double junk = 0.0;
|
|
return bitsToFp((uint64_t)low | ((uint64_t)high << 32), junk);
|
|
}
|
|
|
|
uint32_t
|
|
dblLow(double val) const
|
|
{
|
|
return fpToBits(val);
|
|
}
|
|
|
|
uint32_t
|
|
dblHi(double val) const
|
|
{
|
|
return fpToBits(val) >> 32;
|
|
}
|
|
|
|
template <class fpType>
|
|
fpType
|
|
binaryOp(FPSCR &fpscr, fpType op1, fpType op2,
|
|
fpType (*func)(fpType, fpType),
|
|
bool flush, uint32_t rMode) const
|
|
{
|
|
const bool single = (sizeof(fpType) == sizeof(float));
|
|
fpType junk = 0.0;
|
|
|
|
if (flush && flushToZero(op1, op2))
|
|
fpscr.idc = 1;
|
|
VfpSavedState state = prepFpState(rMode);
|
|
__asm__ __volatile__ ("" : "=m" (op1), "=m" (op2), "=m" (state)
|
|
: "m" (op1), "m" (op2), "m" (state));
|
|
fpType dest = func(op1, op2);
|
|
__asm__ __volatile__ ("" : "=m" (dest) : "m" (dest));
|
|
|
|
int fpClass = std::fpclassify(dest);
|
|
// Get NAN behavior right. This varies between x86 and ARM.
|
|
if (fpClass == FP_NAN) {
|
|
const bool single = (sizeof(fpType) == sizeof(float));
|
|
const uint64_t qnan =
|
|
single ? 0x7fc00000 : ULL(0x7ff8000000000000);
|
|
const bool nan1 = std::isnan(op1);
|
|
const bool nan2 = std::isnan(op2);
|
|
const bool signal1 = nan1 && ((fpToBits(op1) & qnan) != qnan);
|
|
const bool signal2 = nan2 && ((fpToBits(op2) & qnan) != qnan);
|
|
if ((!nan1 && !nan2) || (fpscr.dn == 1)) {
|
|
dest = bitsToFp(qnan, junk);
|
|
} else if (signal1) {
|
|
dest = bitsToFp(fpToBits(op1) | qnan, junk);
|
|
} else if (signal2) {
|
|
dest = bitsToFp(fpToBits(op2) | qnan, junk);
|
|
} else if (nan1) {
|
|
dest = op1;
|
|
} else if (nan2) {
|
|
dest = op2;
|
|
}
|
|
} else if (flush && flushToZero(dest)) {
|
|
feraiseexcept(FeUnderflow);
|
|
} else if ((
|
|
(single && (dest == bitsToFp(0x00800000, junk) ||
|
|
dest == bitsToFp(0x80800000, junk))) ||
|
|
(!single &&
|
|
(dest == bitsToFp(ULL(0x0010000000000000), junk) ||
|
|
dest == bitsToFp(ULL(0x8010000000000000), junk)))
|
|
) && rMode != VfpRoundZero) {
|
|
/*
|
|
* Correct for the fact that underflow is detected -before- rounding
|
|
* in ARM and -after- rounding in x86.
|
|
*/
|
|
fesetround(FeRoundZero);
|
|
__asm__ __volatile__ ("" : "=m" (op1), "=m" (op2)
|
|
: "m" (op1), "m" (op2));
|
|
fpType temp = func(op1, op2);
|
|
__asm__ __volatile__ ("" : "=m" (temp) : "m" (temp));
|
|
if (flush && flushToZero(temp)) {
|
|
dest = temp;
|
|
}
|
|
}
|
|
finishVfp(fpscr, state);
|
|
return dest;
|
|
}
|
|
|
|
template <class fpType>
|
|
fpType
|
|
unaryOp(FPSCR &fpscr, fpType op1,
|
|
fpType (*func)(fpType),
|
|
bool flush, uint32_t rMode) const
|
|
{
|
|
const bool single = (sizeof(fpType) == sizeof(float));
|
|
fpType junk = 0.0;
|
|
|
|
if (flush && flushToZero(op1))
|
|
fpscr.idc = 1;
|
|
VfpSavedState state = prepFpState(rMode);
|
|
__asm__ __volatile__ ("" : "=m" (op1), "=m" (state)
|
|
: "m" (op1), "m" (state));
|
|
fpType dest = func(op1);
|
|
__asm__ __volatile__ ("" : "=m" (dest) : "m" (dest));
|
|
|
|
int fpClass = std::fpclassify(dest);
|
|
// Get NAN behavior right. This varies between x86 and ARM.
|
|
if (fpClass == FP_NAN) {
|
|
const bool single = (sizeof(fpType) == sizeof(float));
|
|
const uint64_t qnan =
|
|
single ? 0x7fc00000 : ULL(0x7ff8000000000000);
|
|
const bool nan = std::isnan(op1);
|
|
if (!nan || fpscr.dn == 1) {
|
|
dest = bitsToFp(qnan, junk);
|
|
} else if (nan) {
|
|
dest = bitsToFp(fpToBits(op1) | qnan, junk);
|
|
}
|
|
} else if (flush && flushToZero(dest)) {
|
|
feraiseexcept(FeUnderflow);
|
|
} else if ((
|
|
(single && (dest == bitsToFp(0x00800000, junk) ||
|
|
dest == bitsToFp(0x80800000, junk))) ||
|
|
(!single &&
|
|
(dest == bitsToFp(ULL(0x0010000000000000), junk) ||
|
|
dest == bitsToFp(ULL(0x8010000000000000), junk)))
|
|
) && rMode != VfpRoundZero) {
|
|
/*
|
|
* Correct for the fact that underflow is detected -before- rounding
|
|
* in ARM and -after- rounding in x86.
|
|
*/
|
|
fesetround(FeRoundZero);
|
|
__asm__ __volatile__ ("" : "=m" (op1) : "m" (op1));
|
|
fpType temp = func(op1);
|
|
__asm__ __volatile__ ("" : "=m" (temp) : "m" (temp));
|
|
if (flush && flushToZero(temp)) {
|
|
dest = temp;
|
|
}
|
|
}
|
|
finishVfp(fpscr, state);
|
|
return dest;
|
|
}
|
|
};
|
|
|
|
class FpRegRegOp : public FpOp
|
|
{
|
|
protected:
|
|
IntRegIndex dest;
|
|
IntRegIndex op1;
|
|
|
|
FpRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
|
|
IntRegIndex _dest, IntRegIndex _op1,
|
|
VfpMicroMode mode = VfpNotAMicroop) :
|
|
FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
|
|
{
|
|
setVfpMicroFlags(mode, flags);
|
|
}
|
|
|
|
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
|
};
|
|
|
|
class FpRegImmOp : public FpOp
|
|
{
|
|
protected:
|
|
IntRegIndex dest;
|
|
uint64_t imm;
|
|
|
|
FpRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
|
|
IntRegIndex _dest, uint64_t _imm,
|
|
VfpMicroMode mode = VfpNotAMicroop) :
|
|
FpOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
|
|
{
|
|
setVfpMicroFlags(mode, flags);
|
|
}
|
|
|
|
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
|
};
|
|
|
|
class FpRegRegImmOp : public FpOp
|
|
{
|
|
protected:
|
|
IntRegIndex dest;
|
|
IntRegIndex op1;
|
|
uint64_t imm;
|
|
|
|
FpRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
|
|
IntRegIndex _dest, IntRegIndex _op1,
|
|
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop) :
|
|
FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), imm(_imm)
|
|
{
|
|
setVfpMicroFlags(mode, flags);
|
|
}
|
|
|
|
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
|
};
|
|
|
|
class FpRegRegRegOp : public FpOp
|
|
{
|
|
protected:
|
|
IntRegIndex dest;
|
|
IntRegIndex op1;
|
|
IntRegIndex op2;
|
|
|
|
FpRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
|
|
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
|
|
VfpMicroMode mode = VfpNotAMicroop) :
|
|
FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2)
|
|
{
|
|
setVfpMicroFlags(mode, flags);
|
|
}
|
|
|
|
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
|
};
|
|
|
|
}
|
|
|
|
#endif //__ARCH_ARM_INSTS_VFP_HH__
|