494 lines
17 KiB
C++
494 lines
17 KiB
C++
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/system/Sequencer.hh"
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#include "mem/ruby/system/System.hh"
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#include "mem/protocol/Protocol.hh"
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#include "mem/ruby/profiler/Profiler.hh"
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#include "mem/ruby/system/CacheMemory.hh"
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#include "mem/protocol/CacheMsg.hh"
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#include "mem/ruby/recorder/Tracer.hh"
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#include "mem/ruby/common/SubBlock.hh"
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#include "mem/protocol/Protocol.hh"
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#include "mem/gems_common/Map.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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//Sequencer::Sequencer(int core_id, MessageBuffer* mandatory_q)
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#define LLSC_FAIL -2
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Sequencer::Sequencer(const string & name)
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:RubyPort(name)
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{
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}
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void Sequencer::init(const vector<string> & argv)
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{
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m_deadlock_check_scheduled = false;
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m_outstanding_count = 0;
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m_max_outstanding_requests = 0;
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m_deadlock_threshold = 0;
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m_version = -1;
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m_instCache_ptr = NULL;
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m_dataCache_ptr = NULL;
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m_controller = NULL;
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for (size_t i=0; i<argv.size(); i+=2) {
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if ( argv[i] == "controller") {
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m_controller = RubySystem::getController(argv[i+1]); // args[i] = "L1Cache"
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m_mandatory_q_ptr = m_controller->getMandatoryQueue();
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} else if ( argv[i] == "icache")
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m_instCache_ptr = RubySystem::getCache(argv[i+1]);
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else if ( argv[i] == "dcache")
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m_dataCache_ptr = RubySystem::getCache(argv[i+1]);
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else if ( argv[i] == "version")
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m_version = atoi(argv[i+1].c_str());
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else if ( argv[i] == "max_outstanding_requests")
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m_max_outstanding_requests = atoi(argv[i+1].c_str());
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else if ( argv[i] == "deadlock_threshold")
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m_deadlock_threshold = atoi(argv[i+1].c_str());
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else {
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cerr << "WARNING: Sequencer: Unkown configuration parameter: " << argv[i] << endl;
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assert(false);
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}
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}
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assert(m_max_outstanding_requests > 0);
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assert(m_deadlock_threshold > 0);
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assert(m_version > -1);
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assert(m_instCache_ptr != NULL);
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assert(m_dataCache_ptr != NULL);
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assert(m_controller != NULL);
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}
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Sequencer::~Sequencer() {
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}
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void Sequencer::wakeup() {
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// Check for deadlock of any of the requests
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Time current_time = g_eventQueue_ptr->getTime();
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// Check across all outstanding requests
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int total_outstanding = 0;
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Vector<Address> keys = m_readRequestTable.keys();
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for (int i=0; i<keys.size(); i++) {
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SequencerRequest* request = m_readRequestTable.lookup(keys[i]);
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if (current_time - request->issue_time >= m_deadlock_threshold) {
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WARN_MSG("Possible Deadlock detected");
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WARN_EXPR(request);
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WARN_EXPR(m_version);
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WARN_EXPR(keys.size());
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WARN_EXPR(current_time);
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WARN_EXPR(request->issue_time);
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WARN_EXPR(current_time - request->issue_time);
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ERROR_MSG("Aborting");
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}
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}
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keys = m_writeRequestTable.keys();
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for (int i=0; i<keys.size(); i++) {
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SequencerRequest* request = m_writeRequestTable.lookup(keys[i]);
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if (current_time - request->issue_time >= m_deadlock_threshold) {
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WARN_MSG("Possible Deadlock detected");
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WARN_EXPR(request);
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WARN_EXPR(m_version);
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WARN_EXPR(current_time);
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WARN_EXPR(request->issue_time);
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WARN_EXPR(current_time - request->issue_time);
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WARN_EXPR(keys.size());
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ERROR_MSG("Aborting");
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}
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}
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total_outstanding += m_writeRequestTable.size() + m_readRequestTable.size();
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assert(m_outstanding_count == total_outstanding);
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if (m_outstanding_count > 0) { // If there are still outstanding requests, keep checking
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g_eventQueue_ptr->scheduleEvent(this, m_deadlock_threshold);
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} else {
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m_deadlock_check_scheduled = false;
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}
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}
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void Sequencer::printProgress(ostream& out) const{
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/*
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int total_demand = 0;
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out << "Sequencer Stats Version " << m_version << endl;
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out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
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out << "---------------" << endl;
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out << "outstanding requests" << endl;
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Vector<Address> rkeys = m_readRequestTable.keys();
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int read_size = rkeys.size();
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out << "proc " << m_version << " Read Requests = " << read_size << endl;
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// print the request table
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for(int i=0; i < read_size; ++i){
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SequencerRequest * request = m_readRequestTable.lookup(rkeys[i]);
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out << "\tRequest[ " << i << " ] = " << request->type << " Address " << rkeys[i] << " Posted " << request->issue_time << " PF " << PrefetchBit_No << endl;
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total_demand++;
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}
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Vector<Address> wkeys = m_writeRequestTable.keys();
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int write_size = wkeys.size();
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out << "proc " << m_version << " Write Requests = " << write_size << endl;
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// print the request table
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for(int i=0; i < write_size; ++i){
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CacheMsg & request = m_writeRequestTable.lookup(wkeys[i]);
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out << "\tRequest[ " << i << " ] = " << request.getType() << " Address " << wkeys[i] << " Posted " << request.getTime() << " PF " << request.getPrefetch() << endl;
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if( request.getPrefetch() == PrefetchBit_No ){
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total_demand++;
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}
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}
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out << endl;
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out << "Total Number Outstanding: " << m_outstanding_count << endl;
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out << "Total Number Demand : " << total_demand << endl;
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out << "Total Number Prefetches : " << m_outstanding_count - total_demand << endl;
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out << endl;
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out << endl;
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*/
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}
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void Sequencer::printConfig(ostream& out) const {
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out << "Seqeuncer config: " << m_name << endl;
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out << " controller: " << m_controller->getName() << endl;
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out << " version: " << m_version << endl;
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out << " max_outstanding_requests: " << m_max_outstanding_requests << endl;
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out << " deadlock_threshold: " << m_deadlock_threshold << endl;
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}
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// Insert the request on the correct request table. Return true if
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// the entry was already present.
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bool Sequencer::insertRequest(SequencerRequest* request) {
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int total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
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assert(m_outstanding_count == total_outstanding);
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// See if we should schedule a deadlock check
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if (m_deadlock_check_scheduled == false) {
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g_eventQueue_ptr->scheduleEvent(this, m_deadlock_threshold);
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m_deadlock_check_scheduled = true;
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}
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Address line_addr(request->ruby_request.paddr);
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line_addr.makeLineAddress();
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if ((request->ruby_request.type == RubyRequestType_ST) ||
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(request->ruby_request.type == RubyRequestType_RMW_Read) ||
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(request->ruby_request.type == RubyRequestType_RMW_Write) ||
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(request->ruby_request.type == RubyRequestType_Locked_Read) ||
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(request->ruby_request.type == RubyRequestType_Locked_Write)) {
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if (m_writeRequestTable.exist(line_addr)) {
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m_writeRequestTable.lookup(line_addr) = request;
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// return true;
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assert(0); // drh5: isn't this an error? do you lose the initial request?
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}
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m_writeRequestTable.allocate(line_addr);
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m_writeRequestTable.lookup(line_addr) = request;
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m_outstanding_count++;
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} else {
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if (m_readRequestTable.exist(line_addr)) {
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m_readRequestTable.lookup(line_addr) = request;
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// return true;
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assert(0); // drh5: isn't this an error? do you lose the initial request?
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}
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m_readRequestTable.allocate(line_addr);
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m_readRequestTable.lookup(line_addr) = request;
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m_outstanding_count++;
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}
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g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
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total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
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assert(m_outstanding_count == total_outstanding);
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return false;
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}
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void Sequencer::removeRequest(SequencerRequest* srequest) {
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assert(m_outstanding_count == m_writeRequestTable.size() + m_readRequestTable.size());
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const RubyRequest & ruby_request = srequest->ruby_request;
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Address line_addr(ruby_request.paddr);
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line_addr.makeLineAddress();
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if ((ruby_request.type == RubyRequestType_ST) ||
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(ruby_request.type == RubyRequestType_RMW_Read) ||
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(ruby_request.type == RubyRequestType_RMW_Write) ||
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(ruby_request.type == RubyRequestType_Locked_Read) ||
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(ruby_request.type == RubyRequestType_Locked_Write)) {
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m_writeRequestTable.deallocate(line_addr);
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} else {
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m_readRequestTable.deallocate(line_addr);
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}
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m_outstanding_count--;
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assert(m_outstanding_count == m_writeRequestTable.size() + m_readRequestTable.size());
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}
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void Sequencer::writeCallback(const Address& address, DataBlock& data) {
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assert(address == line_address(address));
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assert(m_writeRequestTable.exist(line_address(address)));
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SequencerRequest* request = m_writeRequestTable.lookup(address);
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removeRequest(request);
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assert((request->ruby_request.type == RubyRequestType_ST) ||
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(request->ruby_request.type == RubyRequestType_RMW_Read) ||
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(request->ruby_request.type == RubyRequestType_RMW_Write) ||
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(request->ruby_request.type == RubyRequestType_Locked_Read) ||
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(request->ruby_request.type == RubyRequestType_Locked_Write));
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// POLINA: the assumption is that atomics are only on data cache and not instruction cache
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if (request->ruby_request.type == RubyRequestType_Locked_Read) {
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m_dataCache_ptr->setLocked(address, m_version);
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}
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hitCallback(request, data);
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}
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void Sequencer::readCallback(const Address& address, DataBlock& data) {
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assert(address == line_address(address));
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assert(m_readRequestTable.exist(line_address(address)));
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SequencerRequest* request = m_readRequestTable.lookup(address);
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removeRequest(request);
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assert((request->ruby_request.type == RubyRequestType_LD) ||
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(request->ruby_request.type == RubyRequestType_RMW_Read) ||
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(request->ruby_request.type == RubyRequestType_IFETCH));
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hitCallback(request, data);
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}
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void Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data) {
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const RubyRequest & ruby_request = srequest->ruby_request;
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Address request_address(ruby_request.paddr);
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Address request_line_address(ruby_request.paddr);
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request_line_address.makeLineAddress();
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RubyRequestType type = ruby_request.type;
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Time issued_time = srequest->issue_time;
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// Set this cache entry to the most recently used
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if (type == RubyRequestType_IFETCH) {
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if (m_instCache_ptr->isTagPresent(request_line_address) )
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m_instCache_ptr->setMRU(request_line_address);
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} else {
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if (m_dataCache_ptr->isTagPresent(request_line_address) )
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m_dataCache_ptr->setMRU(request_line_address);
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}
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assert(g_eventQueue_ptr->getTime() >= issued_time);
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Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
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// Profile the miss latency for all non-zero demand misses
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if (miss_latency != 0) {
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g_system_ptr->getProfiler()->missLatency(miss_latency, type);
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if (Debug::getProtocolTrace()) {
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g_system_ptr->getProfiler()->profileTransition("Seq", m_version, Address(ruby_request.paddr),
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"", "Done", "", int_to_string(miss_latency)+" cycles");
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}
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}
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/*
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if (request.getPrefetch() == PrefetchBit_Yes) {
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return; // Ignore the prefetch
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}
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*/
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// update the data
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if (ruby_request.data != NULL) {
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if ((type == RubyRequestType_LD) ||
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(type == RubyRequestType_IFETCH) ||
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(type == RubyRequestType_RMW_Read)) {
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memcpy(ruby_request.data, data.getData(request_address.getOffset(), ruby_request.len), ruby_request.len);
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} else {
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data.setData(ruby_request.data, request_address.getOffset(), ruby_request.len);
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}
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}
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m_hit_callback(srequest->id);
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delete srequest;
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}
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// Returns true if the sequencer already has a load or store outstanding
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bool Sequencer::isReady(const RubyRequest& request) const {
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// POLINA: check if we are currently flushing the write buffer, if so Ruby is returned as not ready
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// to simulate stalling of the front-end
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// Do we stall all the sequencers? If it is atomic instruction - yes!
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if (m_outstanding_count >= m_max_outstanding_requests) {
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return false;
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}
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if( m_writeRequestTable.exist(line_address(Address(request.paddr))) ||
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m_readRequestTable.exist(line_address(Address(request.paddr))) ){
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//cout << "OUTSTANDING REQUEST EXISTS " << p << " VER " << m_version << endl;
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//printProgress(cout);
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return false;
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}
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return true;
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}
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bool Sequencer::empty() const {
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return (m_writeRequestTable.size() == 0) && (m_readRequestTable.size() == 0);
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}
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int64_t Sequencer::makeRequest(const RubyRequest & request)
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{
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assert(Address(request.paddr).getOffset() + request.len <= RubySystem::getBlockSizeBytes());
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if (isReady(request)) {
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int64_t id = makeUniqueRequestID();
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SequencerRequest *srequest = new SequencerRequest(request, id, g_eventQueue_ptr->getTime());
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bool found = insertRequest(srequest);
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if (!found)
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if (request.type == RubyRequestType_Locked_Write) {
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// NOTE: it is OK to check the locked flag here as the mandatory queue will be checked first
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// ensuring that nothing comes between checking the flag and servicing the store
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if (!m_dataCache_ptr->isLocked(line_address(Address(request.paddr)), m_version)) {
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return LLSC_FAIL;
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}
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else {
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m_dataCache_ptr->clearLocked(line_address(Address(request.paddr)));
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}
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}
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issueRequest(request);
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// TODO: issue hardware prefetches here
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return id;
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}
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else {
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return -1;
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}
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}
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void Sequencer::issueRequest(const RubyRequest& request) {
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// TODO: get rid of CacheMsg, CacheRequestType, and AccessModeTYpe, & have SLICC use RubyRequest and subtypes natively
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CacheRequestType ctype;
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switch(request.type) {
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case RubyRequestType_IFETCH:
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ctype = CacheRequestType_IFETCH;
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break;
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case RubyRequestType_LD:
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ctype = CacheRequestType_LD;
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break;
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case RubyRequestType_ST:
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ctype = CacheRequestType_ST;
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break;
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case RubyRequestType_Locked_Read:
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ctype = CacheRequestType_ST;
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break;
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case RubyRequestType_Locked_Write:
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ctype = CacheRequestType_ST;
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break;
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case RubyRequestType_RMW_Read:
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ctype = CacheRequestType_ATOMIC;
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break;
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case RubyRequestType_RMW_Write:
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ctype = CacheRequestType_ATOMIC;
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break;
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default:
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assert(0);
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}
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AccessModeType amtype;
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switch(request.access_mode){
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case RubyAccessMode_User:
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amtype = AccessModeType_UserMode;
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break;
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case RubyAccessMode_Supervisor:
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amtype = AccessModeType_SupervisorMode;
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break;
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case RubyAccessMode_Device:
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amtype = AccessModeType_UserMode;
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break;
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default:
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assert(0);
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}
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Address line_addr(request.paddr);
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line_addr.makeLineAddress();
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CacheMsg msg(line_addr, Address(request.paddr), ctype, Address(request.pc), amtype, request.len, PrefetchBit_No);
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if (Debug::getProtocolTrace()) {
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g_system_ptr->getProfiler()->profileTransition("Seq", m_version, Address(request.paddr),
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"", "Begin", "", RubyRequestType_to_string(request.type));
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}
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if (g_system_ptr->getTracer()->traceEnabled()) {
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g_system_ptr->getTracer()->traceRequest(m_name, line_addr, Address(request.pc),
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request.type, g_eventQueue_ptr->getTime());
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}
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Time latency = 0; // initialzed to an null value
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if (request.type == RubyRequestType_IFETCH)
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latency = m_instCache_ptr->getLatency();
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else
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latency = m_dataCache_ptr->getLatency();
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// Send the message to the cache controller
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assert(latency > 0);
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m_mandatory_q_ptr->enqueue(msg, latency);
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}
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/*
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bool Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
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AccessModeType access_mode,
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int size, DataBlock*& data_ptr) {
|
|
if (type == CacheRequestType_IFETCH) {
|
|
return m_instCache_ptr->tryCacheAccess(line_address(addr), type, data_ptr);
|
|
} else {
|
|
return m_dataCache_ptr->tryCacheAccess(line_address(addr), type, data_ptr);
|
|
}
|
|
}
|
|
*/
|
|
|
|
void Sequencer::print(ostream& out) const {
|
|
out << "[Sequencer: " << m_version
|
|
<< ", outstanding requests: " << m_outstanding_count;
|
|
|
|
out << ", read request table: " << m_readRequestTable
|
|
<< ", write request table: " << m_writeRequestTable;
|
|
out << "]";
|
|
}
|
|
|
|
// this can be called from setState whenever coherence permissions are upgraded
|
|
// when invoked, coherence violations will be checked for the given block
|
|
void Sequencer::checkCoherence(const Address& addr) {
|
|
#ifdef CHECK_COHERENCE
|
|
g_system_ptr->checkGlobalCoherenceInvariant(addr);
|
|
#endif
|
|
}
|
|
|