33b28fde7a
This changeset contains a lot of different changes that are too mingled to separate. They are: 1. Added MOESI_CMP_directory I made the changes necessary to bring back MOESI_CMP_directory, including adding a DMA controller. I got rid of MOESI_CMP_directory_m and made MOESI_CMP_directory use a memory controller. Added a new configuration for two level protocols in general, and MOESI_CMP_directory in particular. 2. DMA Sequencer uses a generic SequencerMsg I will eventually make the cache Sequencer use this type as well. It doesn't contain an offset field, just a physical address and a length. MI_example has been updated to deal with this. 3. Parameterized Controllers SLICC controllers can now take custom parameters to use for mapping, latencies, etc. Currently, only int parameters are supported.
241 lines
6.6 KiB
C++
241 lines
6.6 KiB
C++
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PerfectCacheMemory.hh
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*
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* Description:
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*
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* $Id$
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*
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*/
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#ifndef PERFECTCACHEMEMORY_H
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#define PERFECTCACHEMEMORY_H
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#include "mem/ruby/common/Global.hh"
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#include "mem/gems_common/Map.hh"
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#include "mem/protocol/AccessPermission.hh"
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#include "mem/ruby/common/Address.hh"
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template<class ENTRY>
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class PerfectCacheLineState {
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public:
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PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
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AccessPermission m_permission;
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ENTRY m_entry;
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};
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template<class ENTRY>
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extern inline
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ostream& operator<<(ostream& out, const PerfectCacheLineState<ENTRY>& obj)
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{
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return out;
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}
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template<class ENTRY>
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class PerfectCacheMemory {
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public:
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// Constructors
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PerfectCacheMemory();
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// Destructor
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//~PerfectCacheMemory();
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// Public Methods
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static void printConfig(ostream& out);
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// perform a cache access and see if we hit or not. Return true on
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// a hit.
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bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry);
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// tests to see if an address is present in the cache
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bool isTagPresent(const Address& address) const;
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// Returns true if there is:
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// a) a tag match on this address or there is
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// b) an Invalid line in the same cache "way"
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bool cacheAvail(const Address& address) const;
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// find an Invalid entry and sets the tag appropriate for the address
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void allocate(const Address& address);
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void deallocate(const Address& address);
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// Returns with the physical address of the conflicting cache line
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Address cacheProbe(const Address& newAddress) const;
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// looks an address up in the cache
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ENTRY& lookup(const Address& address);
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const ENTRY& lookup(const Address& address) const;
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// Get/Set permission of cache block
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AccessPermission getPermission(const Address& address) const;
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void changePermission(const Address& address, AccessPermission new_perm);
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// Print cache contents
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void print(ostream& out) const;
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private:
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// Private Methods
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// Private copy constructor and assignment operator
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PerfectCacheMemory(const PerfectCacheMemory& obj);
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PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
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// Data Members (m_prefix)
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Map<Address, PerfectCacheLineState<ENTRY> > m_map;
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};
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// Output operator declaration
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//ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj);
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// ******************* Definitions *******************
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// Output operator definition
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template<class ENTRY>
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extern inline
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ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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// ****************************************************************
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template<class ENTRY>
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extern inline
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PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
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{
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}
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// STATIC METHODS
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template<class ENTRY>
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extern inline
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void PerfectCacheMemory<ENTRY>::printConfig(ostream& out)
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{
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}
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// PUBLIC METHODS
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template<class ENTRY>
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extern inline
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bool PerfectCacheMemory<ENTRY>::tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry)
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{
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ERROR_MSG("not implemented");
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}
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// tests to see if an address is present in the cache
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template<class ENTRY>
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extern inline
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bool PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
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{
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return m_map.exist(line_address(address));
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}
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template<class ENTRY>
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extern inline
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bool PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
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{
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return true;
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}
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// find an Invalid or already allocated entry and sets the tag
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// appropriate for the address
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template<class ENTRY>
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extern inline
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void PerfectCacheMemory<ENTRY>::allocate(const Address& address)
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{
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PerfectCacheLineState<ENTRY> line_state;
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line_state.m_permission = AccessPermission_Busy;
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line_state.m_entry = ENTRY();
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m_map.add(line_address(address), line_state);
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}
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// deallocate entry
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template<class ENTRY>
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extern inline
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void PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
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{
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m_map.erase(line_address(address));
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}
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// Returns with the physical address of the conflicting cache line
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template<class ENTRY>
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extern inline
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Address PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
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{
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ERROR_MSG("cacheProbe called in perfect cache");
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}
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// looks an address up in the cache
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template<class ENTRY>
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extern inline
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ENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address)
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{
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return m_map.lookup(line_address(address)).m_entry;
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}
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// looks an address up in the cache
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template<class ENTRY>
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extern inline
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const ENTRY& PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
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{
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return m_map.lookup(line_address(address)).m_entry;
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}
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template<class ENTRY>
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extern inline
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AccessPermission PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
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{
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return m_map.lookup(line_address(address)).m_permission;
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}
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template<class ENTRY>
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extern inline
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void PerfectCacheMemory<ENTRY>::changePermission(const Address& address, AccessPermission new_perm)
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{
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Address line_address = address;
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line_address.makeLineAddress();
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PerfectCacheLineState<ENTRY>& line_state = m_map.lookup(line_address);
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AccessPermission old_perm = line_state.m_permission;
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line_state.m_permission = new_perm;
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}
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template<class ENTRY>
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extern inline
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void PerfectCacheMemory<ENTRY>::print(ostream& out) const
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{
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}
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#endif //PERFECTCACHEMEMORY_H
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