716 lines
18 KiB
C
716 lines
18 KiB
C
/*
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* @DEC_COPYRIGHT@
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*/
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/*
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* HISTORY
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* $Log: tga.h,v $
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* Revision 1.1.1.1 1997/10/30 23:27:18 verghese
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* current 10/29/97
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*
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* Revision 1.1.9.2 1995/04/24 23:34:47 Jeff_Colburn
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* Add support for shared interrupts, ISR's now have a return value
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* of INTR_SERVICED or INTR_NOT_SERVICED. Changed return type from "void"
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* to "int" for interrupt return type in "tga_info_t".
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* [1995/04/24 23:24:12 Jeff_Colburn]
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*
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* Revision 1.1.7.2 1994/11/07 23:31:23 Jeff_Colburn
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* Added defines for putting TGA in Copy mode to support console scrolling fix.
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* [1994/10/26 22:32:00 Jeff_Colburn]
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*
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* Revision 1.1.5.5 1994/05/16 19:29:08 Monty_Brandenberg
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* Add dma_map_info_t to the info struct.
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* [1994/05/12 05:31:19 Monty_Brandenberg]
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*
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* Revision 1.1.5.4 1994/04/19 21:59:33 Stuart_Hollander
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* merge agoshw2 bl5 to gold bl10
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* Revision 1.1.2.4 1994/04/14 20:17:15 Monty_Brandenberg
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* T32-88 Framebuffer offset was incorrect causing obscure z buffering
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* problems in pex.
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* [1994/04/14 19:17:10 Monty_Brandenberg]
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*
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* Revision 1.1.5.3 1994/04/11 12:58:27 Stuart_Hollander
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* Revision 1.1.2.3 1994/02/28 16:53:52 Monty_Brandenberg
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* Removed a few magic numbers from the code and made symbolics out of
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* them.
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* [1994/02/23 21:09:10 Monty_Brandenberg]
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*
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* Add header files we need to define structures. Added two new ioctls
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* to extract direct dma mapping info. SFB+ and TGA ioctl structures
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* are now incompatible. Fixed truecolor index and private ioctl code.
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* [1994/02/04 21:10:07 Monty_Brandenberg]
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*
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* Removed two interrupt sources as per spec. Fixed the RAMDAC access
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* macros to actually work. Imagine.
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* [1994/02/02 23:16:55 Monty_Brandenberg]
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*
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* Converted to use io_handles. Needs work on DMA
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* [1994/01/07 21:14:33 Monty_Brandenberg]
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*
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* Added support for 24-plane option using BT463 and custom cursor chip.
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* Converted to fully prototyped functions. Started conversion to
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* io_handle structure.
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* [1994/01/06 21:15:14 Monty_Brandenberg]
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*
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* Revision 1.1.5.2 1994/01/23 21:16:19 Stuart_Hollander
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* merge from hw2 to goldbl8
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* [1993/12/29 12:57:23 Stuart_Hollander]
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*
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* Revision 1.1.2.2 1993/12/21 13:42:28 Monty_Brandenberg
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* Initial version of the TGA device driver.
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* [1993/12/14 00:22:06 Monty_Brandenberg]
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*
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* $EndLog$
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*/
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/*
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* @(#)$RCSfile: tga.h,v $ $Revision: 1.1.1.1 $ (DEC) $Date: 1997/10/30 23:27:18 $
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*/
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/************************************************************************
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* *
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* Copyright (c) 1993 by *
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* Digital Equipment Corporation, Maynard, MA *
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* All rights reserved. *
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* *
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* This software is furnished under a license and may be used and *
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* copied only in accordance with the terms of such license and *
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* with the inclusion of the above copyright notice. This *
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* software or any other copies thereof may not be provided or *
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* otherwise made available to any other person. No title to and *
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* ownership of the software is hereby transferred. *
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* *
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* The information in this software is subject to change without *
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* notice and should not be construed as a commitment by Digital *
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* Equipment Corporation. *
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* *
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* Digital assumes no responsibility for the use or reliability *
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* of its software on equipment which is not supplied by Digital. *
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* *
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************************************************************************/
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/*
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* RAMDAC is a trademark of Brooktree Corporation
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*/
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#ifndef TGA_DEFINED
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#define TGA_DEFINED
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/*
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* Header files
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*/
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#if 0
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <sys/workstation.h>
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#include <sys/inputdevice.h>
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#include <sys/wsdevice.h>
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#include <io/common/devdriver.h>
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#endif /* 0 */
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/*
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* Special offsets within the PCI configuration header
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*/
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#define TGA_CONFIG_PVRR_OFFSET 0x00000040
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#define TGA_CONFIG_PAER_OFFSET 0x00000044
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/*
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* PAER values
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*/
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#define TGA_CONFIG_PAER_32MB 0x00000000
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#define TGA_CONFIG_PAER_64MB 0x00010000
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#define TGA_CONFIG_PAER_128MB 0x00030000
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/*
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* Offsets within Memory Space
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*/
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#define TGA_ROM_OFFSET 0x000000
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#define TGA_ASIC_OFFSET 0x100000
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#define TGA_RAMDAC_SETUP_OFFSET 0x1000c0
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#define TGA_RAMDAC_DATA_OFFSET 0x1001f0
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#define TGA_XY_REG_OFFSET 0x100074
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#define TGA_VALID_REG_OFFSET 0x100070
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#define TGA_0_0_FB_OFFSET 0x00200000
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#define TGA_0_0_FB_SIZE 0x00200000
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#define TGA_0_1_FB_OFFSET 0x00400000
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#define TGA_0_1_FB_SIZE 0x00400000
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#define TGA_0_3_FB_OFFSET 0x00800000
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#define TGA_0_3_FB_SIZE 0x00800000
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#define TGA_1_3_FB_OFFSET 0x00800000
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#define TGA_1_3_FB_SIZE 0x00800000
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#define TGA_1_7_FB_OFFSET 0x01000000
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#define TGA_1_7_FB_SIZE 0x01000000
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#define TGA_INVALID_FB_OFFSET 0
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#define TGA_INVALID_FB_SIZE 0
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/*
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* TGA card types
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*/
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#define TGA_TYPE_T801 0
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#define TGA_TYPE_T802 1
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#define TGA_TYPE_T822 2
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#define TGA_TYPE_T844 3
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#define TGA_TYPE_T3204 4
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#define TGA_TYPE_T3208 5
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#define TGA_TYPE_T3288 6
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#define TGA_TYPE_INVALID 7
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#define TGA_TYPE_NUM 8
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#ifndef NDEPTHS
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#define NDEPTHS 1 /* all current hardware just has one */
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#define NVISUALS 1
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#endif /* NDEPTHS */
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typedef unsigned char tga_pix8_t;
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typedef unsigned int tga_pix32_t;
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typedef unsigned int tga_reg_t;
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/*
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* Window tags definitions
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*/
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#define TGA_TRUECOLOR_WID_INDEX 0xc
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#define TGA_TRUECOLOR_WID_MASK 0xc0000000
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#if 0
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/*
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* Device-private ioctls
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*/
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#define TGA_IOCTL_PRIVATE _IOWR('w', (0|IOC_S), tga_ioc_t)
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#define TGA_IOC_LOAD_WINDOW_TAGS 0
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#define TGA_IOC_ENABLE_DMA_OPS 1
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#define TGA_IOC_SET_STEREO_MODE 2
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#define TGA_IOC_GET_STEREO_MODE 3
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#define TGA_IOC_GET_DIRECT_DMA_COUNT 4
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#define TGA_IOC_GET_DIRECT_DMA_INFO 5
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typedef struct {
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char windex;
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unsigned char low;
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unsigned char mid;
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unsigned char high;
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} tga_window_tag_cell_t;
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typedef struct {
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short ncells;
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short start;
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tga_window_tag_cell_t *p_cells;
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} tga_ioc_window_tag_t;
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typedef struct {
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vm_offset_t phys_base;
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vm_offset_t bus_base;
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vm_size_t map_size;
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} tga_dma_map_t;
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typedef struct {
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int alloc_map_num; /* input */
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int actual_map_num; /* output */
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tga_dma_map_t *maps; /* input & output */
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} tga_ioc_dma_info_t;
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typedef struct {
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short screen;
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short cmd;
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union {
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tga_ioc_window_tag_t window_tag;
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unsigned int stereo_mode;
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#define TGA_IOC_STEREO_NONE 0
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#define TGA_IOC_STEREO_24 1
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int direct_dma_count;
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tga_ioc_dma_info_t direct_dma_info;
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} data;
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} tga_ioc_t;
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#endif /* 0 */
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typedef struct {
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unsigned deep : 1;
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unsigned mbz0 : 1;
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unsigned mask : 3;
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unsigned block : 4;
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unsigned col_size : 1;
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unsigned sam_size : 1;
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unsigned parity : 1;
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unsigned write_en : 1;
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unsigned ready : 1;
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unsigned slow_dac : 1;
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unsigned dma_size : 1;
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unsigned sync_type : 1;
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unsigned mbz1 : 15;
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} tga_deep_reg_t;
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#define TGA_DEEP_DEEP_8PLANE 0
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#define TGA_DEEP_DEEP_32PLANE 1
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#define TGA_DEEP_MASK_4MB 0x00
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#define TGA_DEEP_MASK_8MB 0x01
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#define TGA_DEEP_MASK_16MB 0x03
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#define TGA_DEEP_MASK_32MB 0x07
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#define TGA_DEEP_PARITY_ODD 0
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#define TGA_DEEP_PARITY_EVEN 1
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#define TGA_DEEP_READY_ON_8 0
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#define TGA_DEEP_READY_ON_2 1
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#define TGA_DEEP_DMA_64 0
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#define TGA_DEEP_DMA_128 1
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typedef struct {
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unsigned s_wr_mask : 8;
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unsigned s_rd_mask : 8;
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unsigned s_test : 3;
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unsigned s_fail : 3;
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unsigned d_fail : 3;
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unsigned d_pass : 3;
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unsigned z_test : 3;
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unsigned z : 1;
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} tga_stencil_mode_reg_t;
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#define TGA_SM_TEST_GEQ 0x00
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#define TGA_SM_TEST_TRUE 0x01
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#define TGA_SM_TEST_FALSE 0x02
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#define TGA_SM_TEST_LS 0x03
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#define TGA_SM_TEST_EQ 0x04
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#define TGA_SM_TEST_LEQ 0x05
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#define TGA_SM_TEST_GT 0x06
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#define TGA_SM_TEST_NEQ 0x07
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#define TGA_SM_RESULT_KEEP 0x00
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#define TGA_SM_RESULT_ZERO 0x01
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#define TGA_SM_RESULT_REPLACE 0x02
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#define TGA_SM_RESULT_INCR 0x03
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#define TGA_SM_RESULT_DECR 0x04
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#define TGA_SM_RESULT_INV 0x05
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#define TGA_SM_Z_REPLACE 0
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#define TGA_SM_Z_KEEP 1
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typedef struct {
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unsigned mode : 8;
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unsigned visual : 3;
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unsigned rotate : 2;
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unsigned line : 1;
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unsigned z16 : 1;
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unsigned cap_ends : 1;
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unsigned mbz : 16;
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} tga_mode_reg_t;
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#define TGA_MODE_MODE_SIMPLE 0x00
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#define TGA_MODE_MODE_Z_SIMPLE 0x10
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#define TGA_MODE_MODE_OPA_STIP 0x01
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#define TGA_MODE_MODE_OPA_FILL 0x21
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#define TGA_MODE_MODE_TRA_STIP 0x05
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#define TGA_MODE_MODE_TRA_FILL 0x25
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#define TGA_MODE_MODE_TRA_BLK_STIP 0x0d
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#define TGA_MODE_MODE_TRA_BLK_FILL 0x2d
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#define TGA_MODE_MODE_OPA_LINE 0x02
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#define TGA_MODE_MODE_TRA_LINE 0x06
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#define TGA_MODE_MODE_CINT_TRA_LINE 0x0e
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#define TGA_MODE_MODE_CINT_TRA_DITH_LINE 0x2e
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#define TGA_MODE_MODE_Z_OPA_LINE 0x12
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#define TGA_MODE_MODE_Z_TRA_LINE 0x16
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#define TGA_MODE_MODE_Z_CINT_OPA_LINE 0x1a
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#define TGA_MODE_MODE_Z_SINT_OPA 0x5a
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#define TGA_MODE_MODE_Z_CINT_OPA_DITH_LINE 0x3a
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#define TGA_MODE_MODE_Z_CINT_TRA_LINE 0x1e
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#define TGA_MODE_MODE_Z_SINT_TRA 0x5e
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#define TGA_MODE_MODE_Z_CINT_TRA_DITH_LINE 0x3e
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#define TGA_MODE_MODE_COPY 0x07
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#define TGA_MODE_MODE_COPY24 0x307
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#define TGA_MODE_MODE_DMA_READ 0x17
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#define TGA_MODE_MODE_DMA_READ_DITH 0x37
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#define TGA_MODE_MODE_DMA_WRITE 0x1f
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#define TGA_MODE_VISUAL_8_PACKED 0x00
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#define TGA_MODE_VISUAL_8_UNPACKED 0x01
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#define TGA_MODE_VISUAL_12_LOW 0x02
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#define TGA_MODE_VISUAL_12_HIGH 0x06
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#define TGA_MODE_VISUAL_24 0x03
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#define TGA_MODE_PM_IS_PERS 0x00800000
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#define TGA_MODE_ADDR_IS_NEW 0x00400000
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#define TGA_MODE_BRES3_IS_NEW 0x00200000
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#define TGA_MODE_COPY_WILL_DRAIN 0x00100000
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typedef struct {
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unsigned opcode : 4;
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unsigned mbz : 4;
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unsigned visual : 2;
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unsigned rotate : 2;
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} tga_raster_op_t;
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#define TGA_ROP_OP_CLEAR 0
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#define TGA_ROP_OP_AND 1
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#define TGA_ROP_OP_AND_REVERSE 2
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#define TGA_ROP_OP_COPY 3
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#define TGA_ROP_OP_COPY24 0x303
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#define TGA_ROP_OP_AND_INVERTED 4
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#define TGA_ROP_OP_NOOP 5
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#define TGA_ROP_OP_XOR 6
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#define TGA_ROP_OP_OR 7
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#define TGA_ROP_OP_NOR 8
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#define TGA_ROP_OP_EQUIV 9
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#define TGA_ROP_OP_INVERT 10
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#define TGA_ROP_OP_OR_REVERSE 11
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#define TGA_ROP_OP_COPY_INVERTED 12
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#define TGA_ROP_OP_OR_INVERTED 13
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#define TGA_ROP_OP_NAND 14
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#define TGA_ROP_OP_SET 15
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#define TGA_ROP_VISUAL_8_PACKED 0x00
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#define TGA_ROP_VISUAL_8_UNPACKED 0x01
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#define TGA_ROP_VISUAL_12 0x02
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#define TGA_ROP_VISUAL_24 0x03
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#define TGA_INTR_VSYNC 0x00000001
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#define TGA_INTR_SHIFT_ADDR 0x00000002
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#define TGA_INTR_TIMER 0x00000010
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#define TGA_INTR_ALL 0x00000013
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#define TGA_INTR_ENABLE_SHIFT 16
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#define TGA_RAMDAC_INTERF_WRITE_SHIFT 0
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#define TGA_RAMDAC_INTERF_READ0_SHIFT 16
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#define TGA_RAMDAC_INTERF_READ1_SHIFT 24
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#define TGA_RAMDAC_485_READ 0x01
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#define TGA_RAMDAC_485_WRITE 0x00
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#define TGA_RAMDAC_485_ADDR_PAL_WRITE 0x00
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#define TGA_RAMDAC_485_DATA_PAL 0x02
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#define TGA_RAMDAC_485_PIXEL_MASK 0x04
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#define TGA_RAMDAC_485_ADDR_PAL_READ 0x06
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#define TGA_RAMDAC_485_ADDR_CUR_WRITE 0x08
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#define TGA_RAMDAC_485_DATA_CUR 0x0a
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#define TGA_RAMDAC_485_CMD_0 0x0c
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#define TGA_RAMDAC_485_ADDR_CUR_READ 0x0e
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#define TGA_RAMDAC_485_CMD_1 0x10
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#define TGA_RAMDAC_485_CMD_2 0x12
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#define TGA_RAMDAC_485_STATUS 0x14
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#define TGA_RAMDAC_485_CMD_3 0x14
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#define TGA_RAMDAC_485_CUR_RAM 0x16
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#define TGA_RAMDAC_485_CUR_LOW_X 0x18
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#define TGA_RAMDAC_485_CUR_HIGH_X 0x1a
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#define TGA_RAMDAC_485_CUR_LOW_Y 0x1c
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#define TGA_RAMDAC_485_CUR_HIGH_Y 0x1e
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#define TGA_RAMDAC_485_ADDR_EPSR_SHIFT 0
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#define TGA_RAMDAC_485_ADDR_EPDR_SHIFT 8
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#define TGA_RAMDAC_463_HEAD_MASK 0x01
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#define TGA_RAMDAC_463_READ 0x02
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#define TGA_RAMDAC_463_WRITE 0x00
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#define TGA_RAMDAC_463_ADDR_LOW 0x00
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#define TGA_RAMDAC_463_ADDR_HIGH 0x04
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#define TGA_RAMDAC_463_CMD_CURS 0x08
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#define TGA_RAMDAC_463_CMD_CMAP 0x0c
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#define TGA_RAMDAC_463_ADDR_EPSR_SHIFT 0
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#define TGA_RAMDAC_463_ADDR_EPDR_SHIFT 8
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#define TGA_RAMDAC_463_CURSOR_COLOR0 0x0100
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#define TGA_RAMDAC_463_CURSOR_COLOR1 0x0101
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#define TGA_RAMDAC_463_COMMAND_REG_0 0x0201
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#define TGA_RAMDAC_463_COMMAND_REG_1 0x0202
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#define TGA_RAMDAC_463_COMMAND_REG_2 0x0203
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#define TGA_RAMDAC_463_READ_MASK 0x0205
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#define TGA_RAMDAC_463_BLINK_MASK 0x0209
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#define TGA_RAMDAC_463_WINDOW_TYPE_TABLE 0x0300
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typedef union {
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struct {
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unsigned int pixels : 9;
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unsigned int front_porch : 5;
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unsigned int sync : 7;
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unsigned int back_porch : 7;
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unsigned int ignore : 3;
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unsigned int odd : 1;
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} horizontal_setup;
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unsigned int h_setup;
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} tga_horizontal_setup_t;
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typedef union {
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struct {
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unsigned int scan_lines : 11;
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unsigned int front_porch : 5;
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unsigned int sync : 6;
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unsigned int back_porch : 6;
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} vertical_setup;
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unsigned int v_setup;
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} tga_vertical_setup_t;
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typedef volatile struct {
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tga_reg_t buffer[8];
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tga_reg_t foreground;
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tga_reg_t background;
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tga_reg_t planemask;
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tga_reg_t pixelmask;
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tga_reg_t mode;
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tga_reg_t rop;
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tga_reg_t shift;
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tga_reg_t address;
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tga_reg_t bres1;
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tga_reg_t bres2;
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tga_reg_t bres3;
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|
tga_reg_t brescont;
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|
tga_reg_t deep;
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|
tga_reg_t start;
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|
tga_reg_t stencil_mode;
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|
tga_reg_t pers_pixelmask;
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|
|
|
tga_reg_t cursor_base_address;
|
|
tga_reg_t horizontal_setup;
|
|
tga_reg_t vertical_setup;
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|
|
|
#define TGA_VERT_STEREO_EN 0x80000000
|
|
tga_reg_t base_address;
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|
tga_reg_t video_valid;
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|
|
|
#define TGA_VIDEO_VALID_SCANNING 0x00000001
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|
#define TGA_VIDEO_VALID_BLANK 0x00000002
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|
#define TGA_VIDEO_VALID_CURSOR_ENABLE 0x00000004
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|
tga_reg_t cursor_xy;
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|
tga_reg_t video_shift_addr;
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|
tga_reg_t intr_status;
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|
|
|
tga_reg_t pixel_data;
|
|
tga_reg_t red_incr;
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|
tga_reg_t green_incr;
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|
tga_reg_t blue_incr;
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|
tga_reg_t z_incr_low;
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|
tga_reg_t z_incr_high;
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|
tga_reg_t dma_address;
|
|
tga_reg_t bres_width;
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|
|
|
tga_reg_t z_value_low;
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|
tga_reg_t z_value_high;
|
|
tga_reg_t z_base_address;
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|
tga_reg_t address2;
|
|
tga_reg_t red_value;
|
|
tga_reg_t green_value;
|
|
tga_reg_t blue_value;
|
|
tga_reg_t _jnk12;
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|
|
|
tga_reg_t ramdac_setup;
|
|
struct {
|
|
tga_reg_t junk;
|
|
} _junk[8 * 2 - 1];
|
|
|
|
struct {
|
|
tga_reg_t data;
|
|
} slope_no_go[8];
|
|
|
|
struct {
|
|
tga_reg_t data;
|
|
} slope[8];
|
|
|
|
tga_reg_t bm_color_0;
|
|
tga_reg_t bm_color_1;
|
|
tga_reg_t bm_color_2;
|
|
tga_reg_t bm_color_3;
|
|
tga_reg_t bm_color_4;
|
|
tga_reg_t bm_color_5;
|
|
tga_reg_t bm_color_6;
|
|
tga_reg_t bm_color_7;
|
|
|
|
tga_reg_t c64_src;
|
|
tga_reg_t c64_dst;
|
|
tga_reg_t c64_src2;
|
|
tga_reg_t c64_dst2;
|
|
tga_reg_t _jnk45;
|
|
tga_reg_t _jnk46;
|
|
tga_reg_t _jnk47;
|
|
tga_reg_t _jnk48;
|
|
|
|
struct {
|
|
tga_reg_t junk;
|
|
} _junk2[8 * 3];
|
|
|
|
tga_reg_t eprom_write;
|
|
tga_reg_t _res0;
|
|
tga_reg_t clock;
|
|
tga_reg_t _res1;
|
|
tga_reg_t ramdac;
|
|
tga_reg_t _res2;
|
|
tga_reg_t command_status;
|
|
tga_reg_t command_status2;
|
|
|
|
}
|
|
tga_rec_t, *tga_ptr_t;
|
|
|
|
#if 0
|
|
typedef struct {
|
|
ws_screen_descriptor screen; /* MUST be first!!! */
|
|
ws_depth_descriptor depth[NDEPTHS];
|
|
ws_visual_descriptor visual[NVISUALS];
|
|
ws_cursor_functions cf;
|
|
ws_color_map_functions cmf;
|
|
ws_screen_functions sf;
|
|
int (*attach)();
|
|
int (*bootmsg)();
|
|
int (*map)();
|
|
int (*interrupt)();
|
|
int (*setup)();
|
|
vm_offset_t base;
|
|
tga_ptr_t asic;
|
|
vm_offset_t fb;
|
|
size_t fb_size;
|
|
unsigned int bt485_present;
|
|
unsigned int bits_per_pixel;
|
|
unsigned int core_size;
|
|
unsigned int paer_value;
|
|
tga_reg_t deep;
|
|
tga_reg_t head_mask;
|
|
tga_reg_t refresh_count;
|
|
tga_reg_t horizontal_setup;
|
|
tga_reg_t vertical_setup;
|
|
tga_reg_t base_address;
|
|
caddr_t info_area;
|
|
vm_offset_t virtual_dma_buffer;
|
|
vm_offset_t physical_dma_buffer;
|
|
int wt_min_dirty;
|
|
int wt_max_dirty;
|
|
int wt_dirty;
|
|
tga_window_tag_cell_t wt_cell[16]; /* magic number */
|
|
unsigned int stereo_mode;
|
|
io_handle_t io_handle;
|
|
dma_map_info_t p_map_info;
|
|
} tga_info_t;
|
|
|
|
#define TGA_USER_MAPPING_COUNT 4
|
|
|
|
typedef struct {
|
|
vm_offset_t fb_alias_increment;
|
|
vm_offset_t option_base;
|
|
unsigned int planemask;
|
|
vm_offset_t virtual_dma_buffer;
|
|
vm_offset_t physical_dma_buffer;
|
|
} tga_server_info_t;
|
|
#endif /* 0 */
|
|
|
|
typedef struct {
|
|
unsigned char dirty_cell;
|
|
unsigned char red; /* only need 8 bits */
|
|
unsigned char green;
|
|
unsigned char blue;
|
|
} tga_bt485_color_cell_t;
|
|
|
|
typedef struct {
|
|
volatile unsigned int *setup;
|
|
volatile unsigned int *data;
|
|
unsigned int head_mask;
|
|
short fb_xoffset;
|
|
short fb_yoffset;
|
|
short min_dirty;
|
|
short max_dirty;
|
|
caddr_t reset;
|
|
u_int mask;
|
|
} tga_bt485_type_t;
|
|
|
|
#if 0
|
|
typedef struct {
|
|
volatile unsigned int *setup;
|
|
volatile unsigned int *data;
|
|
unsigned int head_mask;
|
|
short fb_xoffset;
|
|
short fb_yoffset;
|
|
short min_dirty;
|
|
short max_dirty;
|
|
caddr_t reset;
|
|
u_int mask;
|
|
|
|
/*************************************************************** fields
|
|
* above this line MUST match struct bt485type
|
|
* exactly!***************************************************************/
|
|
u_int unit;
|
|
char screen_on;
|
|
char on_off;
|
|
char dirty_cursor;
|
|
char dirty_colormap;
|
|
short x_hot;
|
|
short y_hot;
|
|
ws_color_cell cursor_fg;
|
|
ws_color_cell cursor_bg;
|
|
void (*enable_interrupt)();
|
|
u_long bits[256];
|
|
tga_bt485_color_cell_t cells[256];
|
|
} tga_bt485_info_t;
|
|
#endif /* 0 */
|
|
|
|
#define TGA_RAMDAC_463_WINDOW_TAG_COUNT 16
|
|
#define TGA_RAMDAC_463_CMAP_ENTRY_COUNT 528
|
|
|
|
typedef struct {
|
|
unsigned char dirty_cell;
|
|
unsigned char red;
|
|
unsigned char green;
|
|
unsigned char blue;
|
|
} tga_bt463_color_cell_t;
|
|
|
|
typedef struct {
|
|
unsigned char low_byte;
|
|
unsigned char middle_byte;
|
|
unsigned char high_byte;
|
|
unsigned char unused;
|
|
} tga_bt463_wid_cell_t;
|
|
|
|
typedef struct {
|
|
volatile unsigned int *setup;
|
|
volatile unsigned int *data;
|
|
unsigned int head_mask;
|
|
short fb_xoffset;
|
|
short fb_yoffset;
|
|
} tga_bt463_type_t;
|
|
|
|
#if 0
|
|
typedef struct {
|
|
volatile unsigned int *setup;
|
|
volatile unsigned int *data;
|
|
unsigned int head_mask;
|
|
short fb_xoffset;
|
|
short fb_yoffset;
|
|
char type;
|
|
char screen_on;
|
|
char dirty_colormap;
|
|
char dirty_cursormap;
|
|
int unit;
|
|
void (*enable_interrupt)();
|
|
caddr_t cursor_closure;
|
|
ws_color_cell cursor_fg;
|
|
ws_color_cell cursor_bg;
|
|
short min_dirty;
|
|
short max_dirty;
|
|
tga_bt463_color_cell_t cells[TGA_RAMDAC_463_CMAP_ENTRY_COUNT];
|
|
} tga_bt463_info_t;
|
|
#endif /* 0 */
|
|
|
|
typedef struct {
|
|
volatile unsigned int *xy_reg;
|
|
volatile unsigned int *valid;
|
|
short fb_xoffset;
|
|
short fb_yoffset;
|
|
} tga_curs_type_t;
|
|
|
|
#if 0
|
|
typedef struct {
|
|
volatile unsigned int *xy_reg;
|
|
volatile unsigned int *valid;
|
|
short fb_xoffset;
|
|
short fb_yoffset;
|
|
u_int unit;
|
|
char on_off;
|
|
char dirty_cursor;
|
|
char dirty_cursormap;
|
|
short x_hot;
|
|
short y_hot;
|
|
short last_row;
|
|
ws_color_cell cursor_fg;
|
|
ws_color_cell cursor_bg;
|
|
void (*enable_interrupt)();
|
|
unsigned int bits[256];
|
|
} tga_curs_info_t;
|
|
#endif /* 0 */
|
|
|
|
#endif /* TGA_DEFINED */
|
|
|