57e07ac2d2
--HG-- rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini rename : tests/long/20.parser/ref/x86/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/x86/linux/simple-atomic/simout => tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini rename : tests/long/20.parser/ref/x86/linux/simple-timing/simerr => tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr rename : tests/long/20.parser/ref/x86/linux/simple-timing/simout => tests/long/se/20.parser/ref/x86/linux/simple-timing/simout rename : tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt rename : tests/long/20.parser/test.py => tests/long/se/20.parser/test.py rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/30.eon/ref/arm/linux/o3-timing/config.ini => tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini rename : tests/long/30.eon/ref/arm/linux/o3-timing/simerr => tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr rename : tests/long/30.eon/ref/arm/linux/o3-timing/simout => tests/long/se/30.eon/ref/arm/linux/o3-timing/simout rename : tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt => tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt rename : tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini => tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini rename : tests/long/30.eon/ref/arm/linux/simple-atomic/simerr => tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr rename : tests/long/30.eon/ref/arm/linux/simple-atomic/simout => tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout rename : tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/30.eon/ref/arm/linux/simple-timing/config.ini => tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini rename : tests/long/30.eon/ref/arm/linux/simple-timing/simerr => tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr rename : tests/long/30.eon/ref/arm/linux/simple-timing/simout => tests/long/se/30.eon/ref/arm/linux/simple-timing/simout rename : tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt => tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt rename : tests/long/30.eon/test.py => tests/long/se/30.eon/test.py rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt rename : tests/long/40.perlbmk/test.py => tests/long/se/40.perlbmk/test.py rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simout => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout rename : tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/50.vortex/test.py => tests/long/se/50.vortex/test.py rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/test.py => tests/long/se/60.bzip2/test.py rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini rename : tests/long/70.twolf/ref/arm/linux/o3-timing/simerr => tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr rename : tests/long/70.twolf/ref/arm/linux/o3-timing/simout => tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout rename : tests/long/70.twolf/ref/arm/linux/o3-timing/smred.out => tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out rename : tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/simout => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/smred.out => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini rename : tests/long/70.twolf/ref/arm/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/arm/linux/simple-timing/simout => tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout rename : tests/long/70.twolf/ref/arm/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out rename : tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simerr => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simout => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.out => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.out rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pin => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pin rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pl1 => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl1 rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl2 rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.sav => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sav rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.sv2 => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sv2 rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.twf => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.twf rename : tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/simout => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.out => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pin => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sav => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini rename : tests/long/70.twolf/ref/x86/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-timing/simout => tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.out rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pin rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sav rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.twf rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/70.twolf/test.py => tests/long/se/70.twolf/test.py rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simout => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout rename : tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/arm/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/arm/linux/simple-timing/simout => tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout rename : tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simout => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout rename : tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/power/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/power/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/power/linux/o3-timing/simout => tests/quick/se/00.hello/ref/power/linux/o3-timing/simout rename : tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt rename : tests/quick/00.hello/test.py => tests/quick/se/00.hello/test.py rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simout => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py
1404 lines
72 KiB
Plaintext
1404 lines
72 KiB
Plaintext
|
|
================ Begin RubySystem Configuration Print ================
|
|
|
|
RubySystem config:
|
|
random_seed: 1234
|
|
randomization: 0
|
|
cycle_period: 1
|
|
block_size_bytes: 64
|
|
block_size_bits: 6
|
|
memory_size_bytes: 134217728
|
|
memory_size_bits: 27
|
|
|
|
Network Configuration
|
|
---------------------
|
|
network: SIMPLE_NETWORK
|
|
topology:
|
|
|
|
virtual_net_0: active, ordered
|
|
virtual_net_1: active, unordered
|
|
virtual_net_2: active, unordered
|
|
virtual_net_3: active, ordered
|
|
virtual_net_4: active, unordered
|
|
virtual_net_5: active, ordered
|
|
virtual_net_6: inactive
|
|
virtual_net_7: inactive
|
|
virtual_net_8: inactive
|
|
virtual_net_9: inactive
|
|
|
|
|
|
Profiler Configuration
|
|
----------------------
|
|
periodic_stats_period: 1000000
|
|
|
|
================ End RubySystem Configuration Print ================
|
|
|
|
|
|
Real time: Jan/23/2012 04:24:27
|
|
|
|
Profiler Stats
|
|
--------------
|
|
Elapsed_time_in_seconds: 120
|
|
Elapsed_time_in_minutes: 2
|
|
Elapsed_time_in_hours: 0.0333333
|
|
Elapsed_time_in_days: 0.00138889
|
|
|
|
Virtual_time_in_seconds: 119.35
|
|
Virtual_time_in_minutes: 1.98917
|
|
Virtual_time_in_hours: 0.0331528
|
|
Virtual_time_in_days: 0.00138137
|
|
|
|
Ruby_current_time: 19658320
|
|
Ruby_start_time: 0
|
|
Ruby_cycles: 19658320
|
|
|
|
mbytes_resident: 41.6445
|
|
mbytes_total: 339.402
|
|
resident_ratio: 0.1227
|
|
|
|
ruby_cycles_executed: [ 19658321 19658321 19658321 19658321 19658321 19658321 19658321 19658321 ]
|
|
|
|
Busy Controller Counts:
|
|
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
|
|
|
L2Cache-0:0
|
|
Directory-0:0
|
|
|
|
|
|
Busy Bank Count:0
|
|
|
|
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 615732 average: 15.9984 | standard deviation: 0.126922 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 615612 ]
|
|
|
|
All Non-Zero Cycle Demand Cache Accesses
|
|
----------------------------------------
|
|
miss_latency: [binsize: 128 max: 18520 count: 615604 average: 4086.79 | standard deviation: 2944.53 | 596 6466 13264 14393 14238 17364 19534 19886 17213 15228 16326 15266 13085 12364 11235 10730 9475 9043 9065 7719 7748 7559 7862 7157 6552 7013 7074 6670 6771 6341 6912 6682 6584 6902 6301 6596 6654 7004 6743 6175 6952 7090 6725 6856 6582 7347 7091 7151 7379 6597 7114 7104 7285 7020 6346 6929 7026 6665 6372 5841 6151 5725 5614 5684 4803 4921 4577 4608 4096 3343 3553 3445 3118 2793 2470 2458 2157 1968 1839 1509 1491 1372 1275 1092 889 849 861 678 630 504 509 471 398 313 303 221 231 191 167 128 129 109 96 89 84 52 62 53 45 29 26 20 18 23 14 13 16 6 7 4 4 2 4 5 2 9 0 1 1 1 1 3 0 0 1 2 1 1 1 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_LD: [binsize: 128 max: 18520 count: 399925 average: 4085.78 | standard deviation: 2943.7 | 411 4241 8744 9371 9204 11299 12636 12913 11096 9899 10485 9918 8546 8048 7413 6933 6133 5806 5894 5034 5021 4872 5059 4679 4204 4555 4577 4358 4446 4076 4496 4395 4244 4508 4111 4303 4337 4576 4392 4020 4619 4630 4439 4337 4254 4804 4601 4590 4875 4227 4658 4573 4693 4557 4183 4441 4623 4325 4101 3776 4035 3686 3683 3683 3151 3218 2947 2959 2688 2200 2281 2233 2025 1848 1629 1589 1388 1243 1160 970 972 871 848 711 556 548 549 449 405 310 346 306 262 198 204 135 149 121 104 87 86 72 63 58 50 38 42 37 28 20 18 15 13 15 9 6 10 2 6 3 2 1 3 5 1 5 0 1 0 1 1 1 0 0 1 2 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_ST: [binsize: 128 max: 17820 count: 215679 average: 4088.66 | standard deviation: 2946.1 | 185 2225 4520 5022 5034 6065 6898 6973 6117 5329 5841 5348 4539 4316 3822 3797 3342 3237 3171 2685 2727 2687 2803 2478 2348 2458 2497 2312 2325 2265 2416 2287 2340 2394 2190 2293 2317 2428 2351 2155 2333 2460 2286 2519 2328 2543 2490 2561 2504 2370 2456 2531 2592 2463 2163 2488 2403 2340 2271 2065 2116 2039 1931 2001 1652 1703 1630 1649 1408 1143 1272 1212 1093 945 841 869 769 725 679 539 519 501 427 381 333 301 312 229 225 194 163 165 136 115 99 86 82 70 63 41 43 37 33 31 34 14 20 16 17 9 8 5 5 8 5 7 6 4 1 1 2 1 1 0 1 4 0 0 1 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_L1Cache: [binsize: 1 max: 2 count: 131 average: 2 | standard deviation: 0 | 0 0 131 ]
|
|
miss_latency_L2Cache: [binsize: 128 max: 14875 count: 3746 average: 4024.34 | standard deviation: 3007.93 | 204 55 53 50 42 111 96 107 106 79 69 84 62 70 71 76 59 59 55 55 58 40 43 38 30 44 37 43 40 53 30 50 48 39 29 37 48 40 46 46 43 40 28 35 34 39 49 48 51 43 34 37 48 27 33 46 34 50 49 30 39 41 26 40 24 29 21 28 21 31 25 22 18 19 12 31 12 10 13 4 10 8 7 2 5 14 4 4 0 5 1 3 2 0 0 4 1 2 0 1 2 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_Directory: [binsize: 128 max: 18520 count: 608513 average: 4090.49 | standard deviation: 2943.6 | 1 6328 13141 14257 14115 17140 19369 19675 17048 15093 16201 15110 12979 12234 11111 10605 9373 8948 8977 7617 7656 7477 7782 7092 6496 6928 6991 6601 6695 6251 6849 6600 6501 6828 6238 6511 6574 6914 6666 6091 6877 7011 6655 6787 6509 7277 7011 7063 7302 6516 7046 7036 7198 6971 6282 6863 6968 6580 6295 5779 6080 5663 5553 5625 4758 4866 4542 4559 4058 3292 3511 3409 3088 2765 2450 2423 2138 1954 1818 1495 1479 1357 1264 1084 879 829 853 671 630 497 506 467 396 312 301 217 229 189 166 127 126 108 95 89 83 52 59 53 44 28 26 20 18 23 14 13 15 5 7 4 4 2 4 5 2 9 0 1 1 1 1 3 0 0 1 2 1 1 1 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_L1Cache_wCC: [binsize: 128 max: 15052 count: 3214 average: 3625.44 | standard deviation: 2955.6 | 260 83 70 86 81 113 69 104 59 56 56 72 44 60 53 49 43 36 33 47 34 42 37 27 26 41 46 26 36 37 33 32 35 35 34 48 32 50 31 38 32 39 42 34 39 31 31 40 26 38 34 31 39 22 31 20 24 35 28 32 32 21 35 19 21 26 14 21 17 20 17 14 12 9 8 4 7 4 8 10 2 7 4 6 5 6 4 3 0 2 2 1 0 1 2 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
imcomplete_wCC_Times: 3214
|
|
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
|
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
|
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
|
miss_latency_dir_first_response_to_completion: [binsize: 4 max: 559 count: 7 average: 349 | standard deviation: 173.877 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
imcomplete_dir_Times: 608506
|
|
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 86 average: 2 | standard deviation: 0 | 0 0 86 ]
|
|
miss_latency_LD_L2Cache: [binsize: 128 max: 14875 count: 2363 average: 3952.27 | standard deviation: 3021.97 | 138 36 38 38 21 71 69 68 68 51 47 56 34 47 47 50 35 39 35 34 38 21 26 23 18 22 23 28 23 30 17 34 30 26 12 16 26 34 31 31 28 25 23 30 23 23 29 25 31 27 17 21 34 13 22 28 18 31 27 21 21 20 18 26 15 20 11 15 13 22 18 12 14 13 6 13 7 7 8 4 7 7 7 1 3 8 2 2 0 2 1 2 2 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_LD_Directory: [binsize: 128 max: 18520 count: 395348 average: 4090.03 | standard deviation: 2942.49 | 0 4146 8658 9278 9133 11157 12522 12773 10991 9808 10400 9813 8481 7963 7331 6853 6072 5743 5837 4969 4966 4821 5007 4640 4165 4510 4530 4311 4405 4020 4459 4342 4193 4458 4075 4256 4288 4508 4339 3960 4567 4580 4387 4287 4204 4758 4553 4542 4825 4173 4616 4533 4635 4531 4144 4401 4590 4272 4051 3734 3993 3654 3641 3648 3123 3177 2928 2929 2667 2166 2255 2210 2001 1827 1620 1572 1377 1232 1146 961 963 859 838 707 549 536 544 445 405 306 343 303 260 197 202 134 147 120 103 86 84 72 62 58 49 38 40 37 27 19 18 15 13 15 9 6 9 2 6 3 2 1 3 5 1 5 0 1 0 1 1 1 0 0 1 2 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 13969 count: 2128 average: 3610.63 | standard deviation: 2983.96 | 187 59 48 55 50 71 45 72 37 40 38 49 31 38 35 30 26 24 22 31 17 30 26 16 21 23 24 19 18 26 20 19 21 24 24 31 23 34 22 29 24 25 29 20 27 23 19 23 19 27 25 19 24 13 17 12 15 22 23 21 21 12 24 9 13 21 8 15 8 12 8 11 10 8 3 4 4 4 6 5 2 5 3 3 4 4 3 2 0 2 2 1 0 1 2 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 45 average: 2 | standard deviation: 0 | 0 0 45 ]
|
|
miss_latency_ST_L2Cache: [binsize: 128 max: 13576 count: 1383 average: 4147.49 | standard deviation: 2980.85 | 66 19 15 12 21 40 27 39 38 28 22 28 28 23 24 26 24 20 20 21 20 19 17 15 12 22 14 15 17 23 13 16 18 13 17 21 22 6 15 15 15 15 5 5 11 16 20 23 20 16 17 16 14 14 11 18 16 19 22 9 18 21 8 14 9 9 10 13 8 9 7 10 4 6 6 18 5 3 5 0 3 1 0 1 2 6 2 2 0 3 0 1 0 0 0 3 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_ST_Directory: [binsize: 128 max: 17820 count: 213165 average: 4091.35 | standard deviation: 2945.66 | 1 2182 4483 4979 4982 5983 6847 6902 6057 5285 5801 5297 4498 4271 3780 3752 3301 3205 3140 2648 2690 2656 2775 2452 2331 2418 2461 2290 2290 2231 2390 2258 2308 2370 2163 2255 2286 2406 2327 2131 2310 2431 2268 2500 2305 2519 2458 2521 2477 2343 2430 2503 2563 2440 2138 2462 2378 2308 2244 2045 2087 2009 1912 1977 1635 1689 1614 1630 1391 1126 1256 1199 1087 938 830 851 761 722 672 534 516 498 426 377 330 293 309 226 225 191 163 164 136 115 99 83 82 69 63 41 42 36 33 31 34 14 19 16 17 9 8 5 5 8 5 7 6 3 1 1 2 1 1 0 1 4 0 0 1 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15052 count: 1086 average: 3654.46 | standard deviation: 2900.39 | 73 24 22 31 31 42 24 32 22 16 18 23 13 22 18 19 17 12 11 16 17 12 11 11 5 18 22 7 18 11 13 13 14 11 10 17 9 16 9 9 8 14 13 14 12 8 12 17 7 11 9 12 15 9 14 8 9 13 5 11 11 9 11 10 8 5 6 6 9 8 9 3 2 1 5 0 3 0 2 5 0 2 1 3 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
|
|
All Non-Zero Cycle SW Prefetch Requests
|
|
------------------------------------
|
|
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
Request vs. RubySystem State Profile
|
|
--------------------------------
|
|
|
|
|
|
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
Message Delayed Cycles
|
|
----------------------
|
|
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
Resource Usage
|
|
--------------
|
|
page_size: 4096
|
|
user_time: 119
|
|
system_time: 0
|
|
page_reclaims: 10999
|
|
page_faults: 0
|
|
swaps: 0
|
|
block_inputs: 0
|
|
block_outputs: 208
|
|
|
|
Network Stats
|
|
-------------
|
|
|
|
total_msg_count_Request_Control: 3688391 29507128
|
|
total_msg_count_Response_Data: 1832355 131929560
|
|
total_msg_count_ResponseL2hit_Data: 4578 329616
|
|
total_msg_count_ResponseLocal_Data: 6687 481464
|
|
total_msg_count_Response_Control: 5517 44136
|
|
total_msg_count_Writeback_Data: 2490666 179327952
|
|
total_msg_count_Writeback_Control: 1184091 9472728
|
|
total_msg_count_Broadcast_Control: 9232425 73859400
|
|
total_msg_count_Persistent_Control: 8208600 65668800
|
|
total_msgs: 26653310 total_bytes: 490620784
|
|
|
|
switch_0_inlinks: 2
|
|
switch_0_outlinks: 2
|
|
links_utilized_percent_switch_0: 3.2394
|
|
links_utilized_percent_switch_0_link_0: 4.18174 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_0_link_1: 2.29707 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_0_link_0_Response_Data: 76720 5523840 [ 0 0 0 0 76720 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_ResponseLocal_Data: 259 18648 [ 0 0 0 0 259 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_Writeback_Data: 82 5904 [ 0 0 0 0 82 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_Broadcast_Control: 538306 4306448 [ 0 538306 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Request_Control: 77189 617512 [ 0 77189 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Response_Data: 124 8928 [ 0 0 0 0 124 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_ResponseLocal_Data: 286 20592 [ 0 0 0 0 286 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Response_Control: 226 1808 [ 0 0 0 0 226 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Writeback_Data: 77037 5546664 [ 0 0 0 0 77037 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Broadcast_Control: 77189 617512 [ 0 77189 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Persistent_Control: 51505 412040 [ 0 0 0 51505 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_1_inlinks: 2
|
|
switch_1_outlinks: 2
|
|
links_utilized_percent_switch_1: 3.23446
|
|
links_utilized_percent_switch_1_link_0: 4.17797 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_1_link_1: 2.29095 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_1_link_0_Response_Data: 76500 5508000 [ 0 0 0 0 76500 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 196 14112 [ 0 0 0 0 196 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_ResponseLocal_Data: 276 19872 [ 0 0 0 0 276 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_Writeback_Data: 109 7848 [ 0 0 0 0 109 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_Broadcast_Control: 538478 4307824 [ 0 538478 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Request_Control: 77017 616136 [ 0 77017 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Response_Data: 132 9504 [ 0 0 0 0 132 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_ResponseLocal_Data: 292 21024 [ 0 0 0 0 292 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Response_Control: 247 1976 [ 0 0 0 0 247 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Writeback_Data: 76832 5531904 [ 0 0 0 0 76832 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Broadcast_Control: 77017 616136 [ 0 77017 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Persistent_Control: 51141 409128 [ 0 0 0 51141 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_2_inlinks: 2
|
|
switch_2_outlinks: 2
|
|
links_utilized_percent_switch_2: 3.2337
|
|
links_utilized_percent_switch_2_link_0: 4.17711 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_2_link_1: 2.29029 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_2_link_0_Response_Data: 76476 5506272 [ 0 0 0 0 76476 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 191 13752 [ 0 0 0 0 191 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_0_ResponseLocal_Data: 247 17784 [ 0 0 0 0 247 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_0_Writeback_Data: 126 9072 [ 0 0 0 0 126 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_0_Broadcast_Control: 538509 4308072 [ 0 538509 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Request_Control: 76986 615888 [ 0 76986 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Response_Data: 118 8496 [ 0 0 0 0 118 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_ResponseLocal_Data: 273 19656 [ 0 0 0 0 273 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Response_Control: 240 1920 [ 0 0 0 0 240 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Writeback_Data: 76800 5529600 [ 0 0 0 0 76800 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Broadcast_Control: 76986 615888 [ 0 76986 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Persistent_Control: 51535 412280 [ 0 0 0 51535 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_3_inlinks: 2
|
|
switch_3_outlinks: 2
|
|
links_utilized_percent_switch_3: 3.24065
|
|
links_utilized_percent_switch_3_link_0: 4.18288 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_3_link_1: 2.29842 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_3_link_0_Response_Data: 76703 5522616 [ 0 0 0 0 76703 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 171 12312 [ 0 0 0 0 171 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_ResponseLocal_Data: 265 19080 [ 0 0 0 0 265 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_Writeback_Data: 183 13176 [ 0 0 0 0 183 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_Broadcast_Control: 538236 4305888 [ 0 538236 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Request_Control: 77259 618072 [ 0 77259 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Response_Data: 116 8352 [ 0 0 0 0 116 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_ResponseLocal_Data: 296 21312 [ 0 0 0 0 296 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Response_Control: 228 1824 [ 0 0 0 0 228 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Writeback_Data: 77093 5550696 [ 0 0 0 0 77093 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Broadcast_Control: 77259 618072 [ 0 77259 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Persistent_Control: 51372 410976 [ 0 0 0 51372 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_4_inlinks: 2
|
|
switch_4_outlinks: 2
|
|
links_utilized_percent_switch_4: 3.22384
|
|
links_utilized_percent_switch_4_link_0: 4.1693 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_4_link_1: 2.27838 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_4_link_0_Response_Data: 75931 5467032 [ 0 0 0 0 75931 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 211 15192 [ 0 0 0 0 211 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_0_ResponseLocal_Data: 287 20664 [ 0 0 0 0 287 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_0_Writeback_Data: 225 16200 [ 0 0 0 0 225 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_0_Broadcast_Control: 538910 4311280 [ 0 538910 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_1_Request_Control: 76585 612680 [ 0 76585 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_1_Response_Data: 129 9288 [ 0 0 0 0 129 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_1_ResponseLocal_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_1_Response_Control: 211 1688 [ 0 0 0 0 211 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_1_Writeback_Data: 76442 5503824 [ 0 0 0 0 76442 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_1_Broadcast_Control: 76585 612680 [ 0 76585 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_4_link_1_Persistent_Control: 51095 408760 [ 0 0 0 51095 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_5_inlinks: 2
|
|
switch_5_outlinks: 2
|
|
links_utilized_percent_switch_5: 3.22911
|
|
links_utilized_percent_switch_5_link_0: 4.17325 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_5_link_1: 2.28497 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_5_link_0_Response_Data: 76128 5481216 [ 0 0 0 0 76128 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 184 13248 [ 0 0 0 0 184 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_0_ResponseLocal_Data: 305 21960 [ 0 0 0 0 305 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_0_Writeback_Data: 231 16632 [ 0 0 0 0 231 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_0_Broadcast_Control: 538720 4309760 [ 0 538720 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_1_Request_Control: 76775 614200 [ 0 76775 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_1_Response_Data: 138 9936 [ 0 0 0 0 138 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_1_ResponseLocal_Data: 274 19728 [ 0 0 0 0 274 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_1_Response_Control: 228 1824 [ 0 0 0 0 228 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_1_Writeback_Data: 76617 5516424 [ 0 0 0 0 76617 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_1_Broadcast_Control: 76775 614200 [ 0 76775 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_5_link_1_Persistent_Control: 51335 410680 [ 0 0 0 51335 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_6_inlinks: 2
|
|
switch_6_outlinks: 2
|
|
links_utilized_percent_switch_6: 3.22368
|
|
links_utilized_percent_switch_6_link_0: 4.16935 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_6_link_1: 2.278 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_6_link_0_Response_Data: 75904 5465088 [ 0 0 0 0 75904 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 201 14472 [ 0 0 0 0 201 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_0_ResponseLocal_Data: 289 20808 [ 0 0 0 0 289 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_0_Writeback_Data: 263 18936 [ 0 0 0 0 263 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_0_Broadcast_Control: 538905 4311240 [ 0 538905 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_1_Request_Control: 76590 612720 [ 0 76590 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_1_Response_Data: 120 8640 [ 0 0 0 0 120 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_1_ResponseLocal_Data: 269 19368 [ 0 0 0 0 269 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_1_Response_Control: 239 1912 [ 0 0 0 0 239 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_1_Writeback_Data: 76419 5502168 [ 0 0 0 0 76419 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_1_Broadcast_Control: 76590 612720 [ 0 76590 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_6_link_1_Persistent_Control: 50944 407552 [ 0 0 0 50944 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_7_inlinks: 2
|
|
switch_7_outlinks: 2
|
|
links_utilized_percent_switch_7: 3.23753
|
|
links_utilized_percent_switch_7_link_0: 4.18018 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_7_link_1: 2.29487 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_7_link_0_Response_Data: 76423 5502456 [ 0 0 0 0 76423 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 168 12096 [ 0 0 0 0 168 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_0_ResponseLocal_Data: 301 21672 [ 0 0 0 0 301 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_0_Writeback_Data: 294 21168 [ 0 0 0 0 294 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_0_Broadcast_Control: 538401 4307208 [ 0 538401 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_Request_Control: 77094 616752 [ 0 77094 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_Response_Data: 108 7776 [ 0 0 0 0 108 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_ResponseLocal_Data: 298 21456 [ 0 0 0 0 298 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_Response_Control: 217 1736 [ 0 0 0 0 217 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_Writeback_Data: 76967 5541624 [ 0 0 0 0 76967 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_Broadcast_Control: 77094 616752 [ 0 77094 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_7_link_1_Persistent_Control: 51503 412024 [ 0 0 0 51503 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_8_inlinks: 2
|
|
switch_8_outlinks: 2
|
|
links_utilized_percent_switch_8: 12.1177
|
|
links_utilized_percent_switch_8_link_0: 16.6607 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_8_link_1: 7.57472 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_8_link_0_Request_Control: 615495 4923960 [ 0 615495 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_0_Response_Control: 1833 14664 [ 0 0 0 0 1833 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_0_Writeback_Data: 613630 44181360 [ 0 0 0 0 613630 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_1_Request_Control: 613969 4911752 [ 0 0 613969 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_1_Response_Data: 1306 94032 [ 0 0 0 0 1306 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 1526 109872 [ 0 0 0 0 1526 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_1_Writeback_Data: 215997 15551784 [ 0 0 0 0 215997 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_8_link_1_Writeback_Control: 394694 3157552 [ 0 0 0 0 394694 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_9_inlinks: 2
|
|
switch_9_outlinks: 2
|
|
links_utilized_percent_switch_9: 11.2311
|
|
links_utilized_percent_switch_9_link_0: 8.53279 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_9_link_1: 13.9295 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_9_link_0_Request_Control: 613968 4911744 [ 0 0 613968 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_9_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_9_link_0_Writeback_Data: 215079 15485688 [ 0 0 0 0 215079 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_9_link_0_Writeback_Control: 394695 3157560 [ 0 0 0 0 394695 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_9_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_9_link_1_Response_Data: 608494 43811568 [ 0 0 0 0 608494 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_9_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_9_link_1_Writeback_Data: 18 1296 [ 0 0 0 0 18 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_9_link_1_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_10_inlinks: 10
|
|
switch_10_outlinks: 10
|
|
links_utilized_percent_switch_10: 5.75614
|
|
links_utilized_percent_switch_10_link_0: 4.05074 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_1: 4.0479 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_2: 4.04603 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_3: 4.05221 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_4: 4.03934 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_5: 4.04268 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_6: 4.03978 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_7: 4.04919 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_8: 16.6607 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_10_link_9: 8.53279 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_10_link_0_Response_Data: 76720 5523840 [ 0 0 0 0 76720 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_0_ResponseLocal_Data: 259 18648 [ 0 0 0 0 259 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_0_Writeback_Data: 82 5904 [ 0 0 0 0 82 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_0_Broadcast_Control: 538306 4306448 [ 0 538306 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_0_Persistent_Control: 358925 2871400 [ 0 0 0 358925 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_1_Response_Data: 76500 5508000 [ 0 0 0 0 76500 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 196 14112 [ 0 0 0 0 196 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_1_ResponseLocal_Data: 276 19872 [ 0 0 0 0 276 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_1_Writeback_Data: 109 7848 [ 0 0 0 0 109 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_1_Broadcast_Control: 538478 4307824 [ 0 538478 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_1_Persistent_Control: 359289 2874312 [ 0 0 0 359289 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_2_Response_Data: 76476 5506272 [ 0 0 0 0 76476 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 191 13752 [ 0 0 0 0 191 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_2_ResponseLocal_Data: 247 17784 [ 0 0 0 0 247 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_2_Writeback_Data: 126 9072 [ 0 0 0 0 126 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_2_Broadcast_Control: 538509 4308072 [ 0 538509 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_2_Persistent_Control: 358895 2871160 [ 0 0 0 358895 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_3_Response_Data: 76703 5522616 [ 0 0 0 0 76703 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 171 12312 [ 0 0 0 0 171 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_3_ResponseLocal_Data: 265 19080 [ 0 0 0 0 265 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_3_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_3_Writeback_Data: 183 13176 [ 0 0 0 0 183 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_3_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_3_Broadcast_Control: 538236 4305888 [ 0 538236 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_3_Persistent_Control: 359058 2872464 [ 0 0 0 359058 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_4_Response_Data: 75931 5467032 [ 0 0 0 0 75931 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 211 15192 [ 0 0 0 0 211 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_4_ResponseLocal_Data: 287 20664 [ 0 0 0 0 287 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_4_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_4_Writeback_Data: 225 16200 [ 0 0 0 0 225 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_4_Broadcast_Control: 538910 4311280 [ 0 538910 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_4_Persistent_Control: 359335 2874680 [ 0 0 0 359335 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_5_Response_Data: 76128 5481216 [ 0 0 0 0 76128 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 184 13248 [ 0 0 0 0 184 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_5_ResponseLocal_Data: 305 21960 [ 0 0 0 0 305 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_5_Writeback_Data: 231 16632 [ 0 0 0 0 231 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_5_Broadcast_Control: 538720 4309760 [ 0 538720 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_5_Persistent_Control: 359095 2872760 [ 0 0 0 359095 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_6_Response_Data: 75904 5465088 [ 0 0 0 0 75904 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 201 14472 [ 0 0 0 0 201 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_6_ResponseLocal_Data: 289 20808 [ 0 0 0 0 289 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_6_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_6_Writeback_Data: 263 18936 [ 0 0 0 0 263 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_6_Broadcast_Control: 538905 4311240 [ 0 538905 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_6_Persistent_Control: 359486 2875888 [ 0 0 0 359486 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_7_Response_Data: 76423 5502456 [ 0 0 0 0 76423 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 168 12096 [ 0 0 0 0 168 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_7_ResponseLocal_Data: 301 21672 [ 0 0 0 0 301 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_7_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_7_Writeback_Data: 294 21168 [ 0 0 0 0 294 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_7_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_7_Broadcast_Control: 538401 4307208 [ 0 538401 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_7_Persistent_Control: 358927 2871416 [ 0 0 0 358927 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_8_Request_Control: 615495 4923960 [ 0 615495 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_8_Response_Control: 1833 14664 [ 0 0 0 0 1833 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_8_Writeback_Data: 613630 44181360 [ 0 0 0 0 613630 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_8_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_9_Request_Control: 613969 4911752 [ 0 0 613969 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_9_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_9_Writeback_Data: 215079 15485688 [ 0 0 0 0 215079 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_9_Writeback_Control: 394695 3157560 [ 0 0 0 0 394695 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_10_link_9_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
|
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
|
|
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
|
|
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
|
system.l1_cntrl0.L1DcacheMemory_total_misses: 77189
|
|
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 77189
|
|
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 65.1557%
|
|
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 34.8443%
|
|
|
|
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 77189 100%
|
|
|
|
--- L1Cache ---
|
|
- Event Counts -
|
|
Load [49690 49997 49629 50054 50303 50190 50006 50073 ] 399942
|
|
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
Store [26905 26796 26976 27053 26903 26845 27007 27200 ] 215685
|
|
Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
L1_Replacement [1281089 1281955 1281461 1287176 1288071 1285927 1285387 1289906 ] 10280972
|
|
Data_Shared [262 248 238 231 241 229 241 222 ] 1912
|
|
Data_Owner [57 66 67 68 67 47 58 64 ] 494
|
|
Data_All_Tokens [76335 76534 76352 76887 76957 76805 76741 77036 ] 613647
|
|
Ack [1 0 1 1 0 1 0 1 ] 5
|
|
Ack_All_Tokens [0 0 0 1 0 0 0 1 ] 2
|
|
Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
Transient_Local_GETX [188736 188850 188667 188589 188743 188802 188643 188443 ] 1509473
|
|
Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
Transient_Local_GETS [350173 349869 350237 349812 349562 349676 349865 349793 ] 2798987
|
|
Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
Transient_Local_GETS_Last_Token [1 1 1 0 1 0 1 0 ] 5
|
|
Persistent_GETX [63290 63349 63338 63218 63414 63370 63215 63283 ] 506477
|
|
Persistent_GETS [117375 117192 117390 117254 117011 117217 117177 117246 ] 937862
|
|
Persistent_GETS_Last_Token [0 0 0 0 0 0 1 0 ] 1
|
|
Own_Lock_or_Unlock [229765 229889 229702 229958 230005 229843 230037 229901 ] 1839100
|
|
Request_Timeout [490512 494638 490301 490311 493060 493644 493295 485817 ] 3931578
|
|
Use_TimeoutStarverX [6 4 5 6 0 3 4 9 ] 37
|
|
Use_TimeoutStarverS [12 18 9 7 5 3 13 9 ] 76
|
|
Use_TimeoutNoStarvers [76249 76442 76272 76789 76882 76734 76675 76961 ] 613004
|
|
Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
|
|
|
|
- Transitions -
|
|
NP Load [49577 49883 49528 49948 50192 50080 49879 49958 ] 399045
|
|
NP Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
NP Store [26838 26735 26909 27000 26843 26777 26936 27143 ] 215181
|
|
NP Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
NP Data_Shared [0 0 0 1 0 0 0 0 ] 1
|
|
NP Data_Owner [4 4 5 8 9 1 8 8 ] 47
|
|
NP Data_All_Tokens [68 70 66 85 68 64 49 57 ] 527
|
|
NP Ack [0 0 0 1 0 0 0 1 ] 2
|
|
NP Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
NP Transient_Local_GETX [188060 188135 187942 187878 188024 188099 187945 187729 ] 1503812
|
|
NP Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
NP Transient_Local_GETS [348916 348636 348950 348528 348293 348374 348601 348501 ] 2788799
|
|
NP Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
NP Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
NP Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
NP Own_Lock_or_Unlock [199095 199187 199157 199216 199244 199357 199305 199312 ] 1593873
|
|
|
|
I Load [0 0 0 0 0 0 0 0 ] 0
|
|
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
I Store [0 0 1 0 0 0 0 1 ] 2
|
|
I Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
I L1_Replacement [211 228 237 217 226 247 239 226 ] 1831
|
|
I Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
|
I Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
|
I Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
|
I Ack [0 0 0 0 0 0 0 0 ] 0
|
|
I Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
I Transient_Local_GETX [2 1 0 0 0 0 0 0 ] 3
|
|
I Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
I Transient_Local_GETS [2 0 0 2 0 1 1 1 ] 7
|
|
I Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
I Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
I Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
I Persistent_GETS [0 1 0 0 0 0 1 0 ] 2
|
|
I Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
I Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
|
|
|
|
S Load [0 0 0 0 0 0 0 0 ] 0
|
|
S Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
S Store [0 0 0 0 0 0 0 0 ] 0
|
|
S Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
S L1_Replacement [319 311 290 284 299 283 290 272 ] 2348
|
|
S Data_Shared [0 0 0 0 0 1 0 1 ] 2
|
|
S Data_Owner [0 1 0 0 0 0 0 0 ] 1
|
|
S Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
|
S Ack [0 0 0 0 0 0 0 0 ] 0
|
|
S Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
S Transient_Local_GETX [0 0 0 0 0 0 1 0 ] 1
|
|
S Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
S Transient_Local_GETS [1 0 0 0 0 0 0 0 ] 1
|
|
S Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
S Transient_Local_GETS_Last_Token [1 1 1 0 1 0 1 0 ] 5
|
|
S Persistent_GETX [0 0 1 0 0 0 0 0 ] 1
|
|
S Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
S Persistent_GETS_Last_Token [0 0 0 0 0 0 1 0 ] 1
|
|
S Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
|
|
|
|
O Load [0 0 0 0 0 0 0 0 ] 0
|
|
O Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
O Store [0 0 0 0 0 0 0 0 ] 0
|
|
O Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
O L1_Replacement [153 182 161 192 182 167 153 188 ] 1378
|
|
O Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
|
O Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
|
O Ack [0 0 0 0 0 0 0 0 ] 0
|
|
O Ack_All_Tokens [0 0 0 0 0 0 0 1 ] 1
|
|
O Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
O Transient_Local_GETX [0 0 0 0 0 0 0 1 ] 1
|
|
O Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
O Transient_Local_GETS [1 0 0 2 0 0 0 0 ] 3
|
|
O Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
O Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
O Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
O Persistent_GETS [0 0 0 0 2 1 0 0 ] 3
|
|
O Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
O Own_Lock_or_Unlock [16 16 25 18 18 10 18 19 ] 140
|
|
|
|
M Load [4 7 7 7 6 6 8 8 ] 53
|
|
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
M Store [2 2 1 1 4 3 7 2 ] 22
|
|
M Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
M L1_Replacement [49126 49389 49077 49486 49717 49626 49450 49528 ] 395399
|
|
M Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
M Transient_Local_GETX [56 69 55 60 63 64 64 45 ] 476
|
|
M Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
M Transient_Local_GETS [100 120 99 133 126 122 103 134 ] 937
|
|
M Persistent_GETX [20 28 27 15 24 31 20 16 ] 181
|
|
M Persistent_GETS [47 54 45 47 52 51 41 43 ] 380
|
|
M Own_Lock_or_Unlock [2949 2916 2889 2948 2917 2850 2824 2858 ] 23151
|
|
|
|
MM Load [3 3 3 2 4 3 4 1 ] 23
|
|
MM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
MM Store [0 3 2 1 2 5 4 1 ] 18
|
|
MM Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
MM L1_Replacement [26772 26662 26820 26911 26761 26690 26850 27040 ] 214506
|
|
MM Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
MM Transient_Local_GETX [30 28 41 35 44 40 37 28 ] 283
|
|
MM Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
MM Transient_Local_GETS [53 57 74 68 53 66 69 88 ] 528
|
|
MM Persistent_GETX [15 14 9 10 15 14 16 16 ] 109
|
|
MM Persistent_GETS [29 20 25 23 26 29 24 23 ] 199
|
|
MM Own_Lock_or_Unlock [1614 1548 1613 1522 1530 1479 1526 1529 ] 12361
|
|
|
|
M_W Load [1 1 1 1 0 1 3 0 ] 8
|
|
M_W Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
M_W Store [0 0 0 1 1 0 0 0 ] 2
|
|
M_W Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
M_W L1_Replacement [220700 219307 219095 219747 220275 220407 219276 220317 ] 1759124
|
|
M_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
M_W Transient_Local_GETX [9 9 11 11 9 9 17 9 ] 84
|
|
M_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
M_W Transient_Local_GETS [23 14 21 21 17 25 24 15 ] 160
|
|
M_W Persistent_GETX [3 2 2 3 0 3 2 7 ] 22
|
|
M_W Persistent_GETS [10 10 8 6 3 3 8 6 ] 54
|
|
M_W Own_Lock_or_Unlock [145 136 179 143 176 142 165 174 ] 1260
|
|
M_W Use_TimeoutStarverX [3 2 3 3 0 3 3 8 ] 25
|
|
M_W Use_TimeoutStarverS [10 10 8 7 4 3 9 8 ] 59
|
|
M_W Use_TimeoutNoStarvers [49352 49663 49304 49742 49987 49897 49685 49768 ] 397398
|
|
M_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
|
|
|
|
MM_W Load [0 0 0 0 0 0 1 1 ] 2
|
|
MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
MM_W Store [0 1 1 0 0 0 0 1 ] 3
|
|
MM_W Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
MM_W L1_Replacement [120344 118153 120667 120138 118740 118451 120032 120021 ] 956546
|
|
MM_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
MM_W Transient_Local_GETX [7 5 5 3 4 9 3 5 ] 41
|
|
MM_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
MM_W Transient_Local_GETS [10 9 14 10 6 13 8 11 ] 81
|
|
MM_W Persistent_GETX [3 1 2 3 0 0 1 1 ] 11
|
|
MM_W Persistent_GETS [2 7 1 0 0 0 4 1 ] 15
|
|
MM_W Own_Lock_or_Unlock [96 78 73 80 92 111 93 104 ] 727
|
|
MM_W Use_TimeoutStarverX [3 2 2 3 0 0 1 1 ] 12
|
|
MM_W Use_TimeoutStarverS [2 8 1 0 1 0 4 1 ] 17
|
|
MM_W Use_TimeoutNoStarvers [26897 26779 26968 27047 26895 26837 26990 27193 ] 215606
|
|
MM_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
|
|
|
|
IM Load [0 0 0 0 0 0 0 0 ] 0
|
|
IM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
IM Store [0 0 0 0 0 0 0 0 ] 0
|
|
IM Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
IM L1_Replacement [301391 304654 304665 306965 304178 304263 304380 303335 ] 2433831
|
|
IM Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
|
IM Data_Owner [0 0 0 1 0 0 0 0 ] 1
|
|
IM Data_All_Tokens [26902 26787 26971 27049 26894 26837 26995 27195 ] 215630
|
|
IM Ack [1 0 1 0 0 1 0 0 ] 3
|
|
IM Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
IM Transient_Local_GETX [81 92 95 92 96 89 75 101 ] 721
|
|
IM Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
IM Transient_Local_GETS [146 170 156 155 165 163 162 147 ] 1264
|
|
IM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
IM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
IM Persistent_GETX [43 52 38 56 39 37 50 38 ] 353
|
|
IM Persistent_GETS [78 85 94 92 56 58 77 65 ] 605
|
|
IM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
IM Own_Lock_or_Unlock [8886 8829 8871 8962 8795 8820 8972 8897 ] 71032
|
|
IM Request_Timeout [173243 171251 171891 171981 171016 170371 172749 170073 ] 1372575
|
|
|
|
SM Load [0 0 0 0 0 0 0 0 ] 0
|
|
SM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
SM Store [0 0 0 0 0 0 0 0 ] 0
|
|
SM Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
|
SM Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
|
SM Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
|
SM Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
|
SM Ack [0 0 0 0 0 0 0 0 ] 0
|
|
SM Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
SM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
SM Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
SM Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
SM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
SM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
SM Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
SM Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
SM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
SM Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
|
|
SM Request_Timeout [0 0 0 0 0 0 0 0 ] 0
|
|
|
|
OM Load [0 0 0 0 0 0 0 0 ] 0
|
|
OM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
OM Store [0 0 0 0 0 0 0 0 ] 0
|
|
OM Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
OM L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
|
OM Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
|
OM Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
|
OM Ack [0 0 0 0 0 0 0 0 ] 0
|
|
OM Ack_All_Tokens [0 0 0 1 0 0 0 0 ] 1
|
|
OM Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
OM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
OM Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
OM Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
OM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
OM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
OM Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
OM Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
OM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
OM Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
|
|
OM Request_Timeout [0 0 0 0 0 0 0 0 ] 0
|
|
|
|
IS Load [0 0 0 0 0 0 0 0 ] 0
|
|
IS Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
IS Store [0 0 0 0 0 0 0 0 ] 0
|
|
IS Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
IS L1_Replacement [558391 559786 557026 559859 565174 562983 561754 565799 ] 4490772
|
|
IS Data_Shared [262 248 238 230 241 228 241 221 ] 1909
|
|
IS Data_Owner [53 61 62 59 58 46 50 56 ] 445
|
|
IS Data_All_Tokens [49365 49675 49314 49752 49992 49903 49695 49781 ] 397477
|
|
IS Ack [0 0 0 0 0 0 0 0 ] 0
|
|
IS Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
IS Transient_Local_GETX [152 165 194 154 155 145 162 176 ] 1303
|
|
IS Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
IS Transient_Local_GETS [307 263 305 268 293 329 302 280 ] 2347
|
|
IS Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
IS Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
IS Persistent_GETX [74 71 106 80 51 70 64 83 ] 599
|
|
IS Persistent_GETS [161 147 137 141 126 112 141 118 ] 1083
|
|
IS Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
IS Own_Lock_or_Unlock [16309 16529 16248 16447 16685 16505 16513 16434 ] 131670
|
|
IS Request_Timeout [313059 320314 315804 315404 319222 320475 317516 312314 ] 2534108
|
|
|
|
I_L Load [105 103 90 96 101 100 111 105 ] 811
|
|
I_L Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
I_L Store [65 55 62 50 53 60 60 52 ] 457
|
|
I_L Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
I_L L1_Replacement [25 126 71 53 116 66 12 64 ] 533
|
|
I_L Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
|
I_L Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
|
I_L Data_All_Tokens [0 0 0 0 1 1 0 0 ] 2
|
|
I_L Ack [0 0 0 0 0 0 0 0 ] 0
|
|
I_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
I_L Transient_Local_GETX [339 346 324 355 348 347 338 348 ] 2745
|
|
I_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
I_L Transient_Local_GETS [612 599 617 623 607 583 593 613 ] 4847
|
|
I_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
I_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
I_L Persistent_GETX [63107 63144 63106 63004 63284 63208 63045 63090 ] 504988
|
|
I_L Persistent_GETS [116967 116795 117007 116853 116744 116946 116855 116933 ] 935100
|
|
I_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
I_L Own_Lock_or_Unlock [72 75 68 54 66 77 69 65 ] 546
|
|
|
|
S_L Load [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Store [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
S_L L1_Replacement [0 32 14 9 5 4 36 16 ] 116
|
|
S_L Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Ack [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Persistent_GETS [8 9 6 7 0 0 3 7 ] 40
|
|
S_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
S_L Own_Lock_or_Unlock [57 64 53 54 58 55 51 51 ] 443
|
|
|
|
IM_L Load [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L Store [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L L1_Replacement [1324 1203 1265 1139 949 800 1068 1198 ] 8946
|
|
IM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L Data_All_Tokens [0 2 0 0 1 0 0 0 ] 3
|
|
IM_L Ack [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L Transient_Local_GETX [0 0 0 0 0 0 1 0 ] 1
|
|
IM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L Transient_Local_GETS [0 0 1 0 0 0 1 1 ] 3
|
|
IM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
IM_L Persistent_GETX [10 17 13 21 0 0 3 10 ] 74
|
|
IM_L Persistent_GETS [29 21 28 30 1 6 6 17 ] 138
|
|
IM_L Own_Lock_or_Unlock [186 190 194 198 147 155 187 155 ] 1412
|
|
IM_L Request_Timeout [1228 1042 1147 1157 934 789 1235 918 ] 8450
|
|
|
|
SM_L Load [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Store [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Ack [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
|
|
SM_L Request_Timeout [0 0 0 0 0 0 0 0 ] 0
|
|
|
|
IS_L Load [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L Ifetch [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L Store [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L Atomic [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L L1_Replacement [2333 1922 2073 2176 1449 1940 1847 1902 ] 15642
|
|
IS_L Data_Shared [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L Data_Owner [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L Data_All_Tokens [0 0 1 1 1 0 2 3 ] 8
|
|
IS_L Ack [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L Transient_Local_GETX [0 0 0 1 0 0 0 1 ] 2
|
|
IS_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L Transient_Local_GETS [2 1 0 2 2 0 1 2 ] 10
|
|
IS_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
|
|
IS_L Persistent_GETX [15 20 34 26 1 7 14 22 ] 139
|
|
IS_L Persistent_GETS [44 43 39 55 1 11 17 33 ] 243
|
|
IS_L Own_Lock_or_Unlock [340 321 332 316 277 282 314 303 ] 2485
|
|
IS_L Request_Timeout [2982 2031 1459 1769 1888 2009 1795 2512 ] 16445
|
|
|
|
Cache Stats: system.l1_cntrl1.L1IcacheMemory
|
|
system.l1_cntrl1.L1IcacheMemory_total_misses: 0
|
|
system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0
|
|
system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
Cache Stats: system.l1_cntrl1.L1DcacheMemory
|
|
system.l1_cntrl1.L1DcacheMemory_total_misses: 77017
|
|
system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 77017
|
|
system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl1.L1DcacheMemory_request_type_LD: 65.1544%
|
|
system.l1_cntrl1.L1DcacheMemory_request_type_ST: 34.8456%
|
|
|
|
system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 77017 100%
|
|
|
|
Cache Stats: system.l1_cntrl2.L1IcacheMemory
|
|
system.l1_cntrl2.L1IcacheMemory_total_misses: 0
|
|
system.l1_cntrl2.L1IcacheMemory_total_demand_misses: 0
|
|
system.l1_cntrl2.L1IcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl2.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl2.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
Cache Stats: system.l1_cntrl2.L1DcacheMemory
|
|
system.l1_cntrl2.L1DcacheMemory_total_misses: 76986
|
|
system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76986
|
|
system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl2.L1DcacheMemory_request_type_LD: 64.9339%
|
|
system.l1_cntrl2.L1DcacheMemory_request_type_ST: 35.0661%
|
|
|
|
system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 76986 100%
|
|
|
|
Cache Stats: system.l1_cntrl3.L1IcacheMemory
|
|
system.l1_cntrl3.L1IcacheMemory_total_misses: 0
|
|
system.l1_cntrl3.L1IcacheMemory_total_demand_misses: 0
|
|
system.l1_cntrl3.L1IcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl3.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl3.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
Cache Stats: system.l1_cntrl3.L1DcacheMemory
|
|
system.l1_cntrl3.L1DcacheMemory_total_misses: 77259
|
|
system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 77259
|
|
system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl3.L1DcacheMemory_request_type_LD: 64.7989%
|
|
system.l1_cntrl3.L1DcacheMemory_request_type_ST: 35.2011%
|
|
|
|
system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 77259 100%
|
|
|
|
Cache Stats: system.l1_cntrl4.L1IcacheMemory
|
|
system.l1_cntrl4.L1IcacheMemory_total_misses: 0
|
|
system.l1_cntrl4.L1IcacheMemory_total_demand_misses: 0
|
|
system.l1_cntrl4.L1IcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl4.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl4.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
Cache Stats: system.l1_cntrl4.L1DcacheMemory
|
|
system.l1_cntrl4.L1DcacheMemory_total_misses: 76585
|
|
system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76585
|
|
system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.8717%
|
|
system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.1283%
|
|
|
|
system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 76585 100%
|
|
|
|
Cache Stats: system.l1_cntrl5.L1IcacheMemory
|
|
system.l1_cntrl5.L1IcacheMemory_total_misses: 0
|
|
system.l1_cntrl5.L1IcacheMemory_total_demand_misses: 0
|
|
system.l1_cntrl5.L1IcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl5.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl5.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
Cache Stats: system.l1_cntrl5.L1DcacheMemory
|
|
system.l1_cntrl5.L1DcacheMemory_total_misses: 76776
|
|
system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76776
|
|
system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl5.L1DcacheMemory_request_type_LD: 65.1063%
|
|
system.l1_cntrl5.L1DcacheMemory_request_type_ST: 34.8937%
|
|
|
|
system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 76776 100%
|
|
|
|
Cache Stats: system.l1_cntrl6.L1IcacheMemory
|
|
system.l1_cntrl6.L1IcacheMemory_total_misses: 0
|
|
system.l1_cntrl6.L1IcacheMemory_total_demand_misses: 0
|
|
system.l1_cntrl6.L1IcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl6.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl6.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
Cache Stats: system.l1_cntrl6.L1DcacheMemory
|
|
system.l1_cntrl6.L1DcacheMemory_total_misses: 76590
|
|
system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76590
|
|
system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.7839%
|
|
system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.2161%
|
|
|
|
system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 76590 100%
|
|
|
|
Cache Stats: system.l1_cntrl7.L1IcacheMemory
|
|
system.l1_cntrl7.L1IcacheMemory_total_misses: 0
|
|
system.l1_cntrl7.L1IcacheMemory_total_demand_misses: 0
|
|
system.l1_cntrl7.L1IcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl7.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl7.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
Cache Stats: system.l1_cntrl7.L1DcacheMemory
|
|
system.l1_cntrl7.L1DcacheMemory_total_misses: 77094
|
|
system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 77094
|
|
system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l1_cntrl7.L1DcacheMemory_request_type_LD: 64.913%
|
|
system.l1_cntrl7.L1DcacheMemory_request_type_ST: 35.087%
|
|
|
|
system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 77094 100%
|
|
|
|
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
|
system.l2_cntrl0.L2cacheMemory_total_misses: 613969
|
|
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 613969
|
|
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
|
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
|
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
|
|
|
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 64.9684%
|
|
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 35.0316%
|
|
|
|
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 613969 100%
|
|
|
|
--- L2Cache ---
|
|
- Event Counts -
|
|
L1_GETS [399854 ] 399854
|
|
L1_GETS_Last_Token [2 ] 2
|
|
L1_GETX [215639 ] 215639
|
|
L1_INV [1833 ] 1833
|
|
Transient_GETX [0 ] 0
|
|
Transient_GETS [0 ] 0
|
|
Transient_GETS_Last_Token [0 ] 0
|
|
L2_Replacement [610216 ] 610216
|
|
Writeback_Tokens [0 ] 0
|
|
Writeback_Shared_Data [1536 ] 1536
|
|
Writeback_All_Tokens [610964 ] 610964
|
|
Writeback_Owned [1130 ] 1130
|
|
Data_Shared [0 ] 0
|
|
Data_Owner [0 ] 0
|
|
Data_All_Tokens [0 ] 0
|
|
Ack [0 ] 0
|
|
Ack_All_Tokens [0 ] 0
|
|
Persistent_GETX [72354 ] 72354
|
|
Persistent_GETS [133978 ] 133978
|
|
Persistent_GETS_Last_Token [2 ] 2
|
|
Own_Lock_or_Unlock [204096 ] 204096
|
|
|
|
- Transitions -
|
|
NP L1_GETS [398076 ] 398076
|
|
NP L1_GETX [214623 ] 214623
|
|
NP L1_INV [1288 ] 1288
|
|
NP Transient_GETX [0 ] 0
|
|
NP Transient_GETS [0 ] 0
|
|
NP Writeback_Tokens [0 ] 0
|
|
NP Writeback_Shared_Data [1529 ] 1529
|
|
NP Writeback_All_Tokens [607613 ] 607613
|
|
NP Writeback_Owned [1082 ] 1082
|
|
NP Data_Shared [0 ] 0
|
|
NP Data_Owner [0 ] 0
|
|
NP Data_All_Tokens [0 ] 0
|
|
NP Ack [0 ] 0
|
|
NP Persistent_GETX [0 ] 0
|
|
NP Persistent_GETS [0 ] 0
|
|
NP Persistent_GETS_Last_Token [0 ] 0
|
|
NP Own_Lock_or_Unlock [203275 ] 203275
|
|
|
|
I L1_GETS [1 ] 1
|
|
I L1_GETS_Last_Token [0 ] 0
|
|
I L1_GETX [0 ] 0
|
|
I L1_INV [1 ] 1
|
|
I Transient_GETX [0 ] 0
|
|
I Transient_GETS [0 ] 0
|
|
I Transient_GETS_Last_Token [0 ] 0
|
|
I L2_Replacement [533 ] 533
|
|
I Writeback_Tokens [0 ] 0
|
|
I Writeback_Shared_Data [1 ] 1
|
|
I Writeback_All_Tokens [846 ] 846
|
|
I Writeback_Owned [0 ] 0
|
|
I Data_Shared [0 ] 0
|
|
I Data_Owner [0 ] 0
|
|
I Data_All_Tokens [0 ] 0
|
|
I Ack [0 ] 0
|
|
I Persistent_GETX [0 ] 0
|
|
I Persistent_GETS [0 ] 0
|
|
I Persistent_GETS_Last_Token [0 ] 0
|
|
I Own_Lock_or_Unlock [0 ] 0
|
|
|
|
S L1_GETS [1 ] 1
|
|
S L1_GETS_Last_Token [2 ] 2
|
|
S L1_GETX [1 ] 1
|
|
S L1_INV [0 ] 0
|
|
S Transient_GETX [0 ] 0
|
|
S Transient_GETS [0 ] 0
|
|
S Transient_GETS_Last_Token [0 ] 0
|
|
S L2_Replacement [1276 ] 1276
|
|
S Writeback_Tokens [0 ] 0
|
|
S Writeback_Shared_Data [0 ] 0
|
|
S Writeback_All_Tokens [248 ] 248
|
|
S Writeback_Owned [1 ] 1
|
|
S Data_Shared [0 ] 0
|
|
S Data_Owner [0 ] 0
|
|
S Data_All_Tokens [0 ] 0
|
|
S Ack [0 ] 0
|
|
S Persistent_GETX [0 ] 0
|
|
S Persistent_GETS [0 ] 0
|
|
S Persistent_GETS_Last_Token [2 ] 2
|
|
S Own_Lock_or_Unlock [0 ] 0
|
|
|
|
O L1_GETS [4 ] 4
|
|
O L1_GETS_Last_Token [0 ] 0
|
|
O L1_GETX [0 ] 0
|
|
O L1_INV [0 ] 0
|
|
O Transient_GETX [0 ] 0
|
|
O Transient_GETS [0 ] 0
|
|
O Transient_GETS_Last_Token [0 ] 0
|
|
O L2_Replacement [1234 ] 1234
|
|
O Writeback_Tokens [0 ] 0
|
|
O Writeback_Shared_Data [5 ] 5
|
|
O Writeback_All_Tokens [812 ] 812
|
|
O Data_Shared [0 ] 0
|
|
O Data_All_Tokens [0 ] 0
|
|
O Ack [0 ] 0
|
|
O Ack_All_Tokens [0 ] 0
|
|
O Persistent_GETX [0 ] 0
|
|
O Persistent_GETS [0 ] 0
|
|
O Persistent_GETS_Last_Token [0 ] 0
|
|
O Own_Lock_or_Unlock [0 ] 0
|
|
|
|
M L1_GETS [963 ] 963
|
|
M L1_GETX [556 ] 556
|
|
M L1_INV [0 ] 0
|
|
M Transient_GETX [0 ] 0
|
|
M Transient_GETS [0 ] 0
|
|
M L2_Replacement [606686 ] 606686
|
|
M Persistent_GETX [487 ] 487
|
|
M Persistent_GETS [819 ] 819
|
|
M Own_Lock_or_Unlock [0 ] 0
|
|
|
|
I_L L1_GETS [809 ] 809
|
|
I_L L1_GETX [459 ] 459
|
|
I_L L1_INV [544 ] 544
|
|
I_L Transient_GETX [0 ] 0
|
|
I_L Transient_GETS [0 ] 0
|
|
I_L Transient_GETS_Last_Token [0 ] 0
|
|
I_L L2_Replacement [485 ] 485
|
|
I_L Writeback_Tokens [0 ] 0
|
|
I_L Writeback_Shared_Data [1 ] 1
|
|
I_L Writeback_All_Tokens [1445 ] 1445
|
|
I_L Writeback_Owned [47 ] 47
|
|
I_L Data_Shared [0 ] 0
|
|
I_L Data_Owner [0 ] 0
|
|
I_L Data_All_Tokens [0 ] 0
|
|
I_L Ack [0 ] 0
|
|
I_L Persistent_GETX [71867 ] 71867
|
|
I_L Persistent_GETS [133159 ] 133159
|
|
I_L Own_Lock_or_Unlock [821 ] 821
|
|
|
|
S_L L1_GETS [0 ] 0
|
|
S_L L1_GETS_Last_Token [0 ] 0
|
|
S_L L1_GETX [0 ] 0
|
|
S_L L1_INV [0 ] 0
|
|
S_L Transient_GETX [0 ] 0
|
|
S_L Transient_GETS [0 ] 0
|
|
S_L Transient_GETS_Last_Token [0 ] 0
|
|
S_L L2_Replacement [2 ] 2
|
|
S_L Writeback_Tokens [0 ] 0
|
|
S_L Writeback_Shared_Data [0 ] 0
|
|
S_L Writeback_All_Tokens [0 ] 0
|
|
S_L Writeback_Owned [0 ] 0
|
|
S_L Data_Shared [0 ] 0
|
|
S_L Data_Owner [0 ] 0
|
|
S_L Data_All_Tokens [0 ] 0
|
|
S_L Ack [0 ] 0
|
|
S_L Persistent_GETX [0 ] 0
|
|
S_L Persistent_GETS [0 ] 0
|
|
S_L Persistent_GETS_Last_Token [0 ] 0
|
|
S_L Own_Lock_or_Unlock [0 ] 0
|
|
|
|
Memory controller: system.dir_cntrl0.memBuffer:
|
|
memory_total_requests: 823553
|
|
memory_reads: 608473
|
|
memory_writes: 215049
|
|
memory_refreshes: 40955
|
|
memory_total_request_delays: 49483061
|
|
memory_delays_per_request: 60.0849
|
|
memory_delays_in_input_queue: 412614
|
|
memory_delays_behind_head_of_bank_queue: 20169004
|
|
memory_delays_stalled_at_head_of_bank_queue: 28901443
|
|
memory_stalls_for_bank_busy: 4444487
|
|
memory_stalls_for_random_busy: 0
|
|
memory_stalls_for_anti_starvation: 6925202
|
|
memory_stalls_for_arbitration: 5968951
|
|
memory_stalls_for_bus: 8105541
|
|
memory_stalls_for_tfaw: 0
|
|
memory_stalls_for_read_write_turnaround: 2060025
|
|
memory_stalls_for_read_read_turnaround: 1397237
|
|
accesses_per_bank: 25898 25514 25666 25899 25982 25832 26034 25723 25946 25743 25754 25919 25502 25605 25766 25591 25671 25693 25738 25726 25790 25650 25833 25622 25617 25329 25704 25328 25634 25911 26070 25863
|
|
|
|
--- Directory ---
|
|
- Event Counts -
|
|
GETX [402036 ] 402036
|
|
GETS [737914 ] 737914
|
|
Lockdown [206334 ] 206334
|
|
Unlockdown [204096 ] 204096
|
|
Own_Lock_or_Unlock [0 ] 0
|
|
Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
Data_Owner [210 ] 210
|
|
Data_All_Tokens [214914 ] 214914
|
|
Ack_Owner [665 ] 665
|
|
Ack_Owner_All_Tokens [392751 ] 392751
|
|
Tokens [512 ] 512
|
|
Ack_All_Tokens [8723 ] 8723
|
|
Request_Timeout [0 ] 0
|
|
Memory_Data [608472 ] 608472
|
|
Memory_Ack [215045 ] 215045
|
|
DMA_READ [0 ] 0
|
|
DMA_WRITE [0 ] 0
|
|
DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
- Transitions -
|
|
O GETX [211925 ] 211925
|
|
O GETS [393078 ] 393078
|
|
O Lockdown [1855 ] 1855
|
|
O Unlockdown [0 ] 0
|
|
O Own_Lock_or_Unlock [0 ] 0
|
|
O Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
O Data_Owner [0 ] 0
|
|
O Data_All_Tokens [1 ] 1
|
|
O Tokens [1 ] 1
|
|
O Ack_All_Tokens [867 ] 867
|
|
O DMA_READ [0 ] 0
|
|
O DMA_WRITE [0 ] 0
|
|
O DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
NO GETX [1680 ] 1680
|
|
NO GETS [3187 ] 3187
|
|
NO Lockdown [8635 ] 8635
|
|
NO Unlockdown [0 ] 0
|
|
NO Own_Lock_or_Unlock [0 ] 0
|
|
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
NO Data_Owner [210 ] 210
|
|
NO Data_All_Tokens [214850 ] 214850
|
|
NO Ack_Owner [665 ] 665
|
|
NO Ack_Owner_All_Tokens [392729 ] 392729
|
|
NO Tokens [410 ] 410
|
|
NO DMA_READ [0 ] 0
|
|
NO DMA_WRITE [0 ] 0
|
|
|
|
L GETX [1478 ] 1478
|
|
L GETS [2620 ] 2620
|
|
L Lockdown [1289 ] 1289
|
|
L Unlockdown [204096 ] 204096
|
|
L Own_Lock_or_Unlock [0 ] 0
|
|
L Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
L Data_Owner [0 ] 0
|
|
L Data_All_Tokens [18 ] 18
|
|
L Ack_Owner [0 ] 0
|
|
L Ack_Owner_All_Tokens [22 ] 22
|
|
L Tokens [2 ] 2
|
|
L DMA_READ [0 ] 0
|
|
L DMA_WRITE [0 ] 0
|
|
L DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
O_W GETX [47833 ] 47833
|
|
O_W GETS [90041 ] 90041
|
|
O_W Lockdown [1635 ] 1635
|
|
O_W Unlockdown [0 ] 0
|
|
O_W Own_Lock_or_Unlock [0 ] 0
|
|
O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
O_W Data_Owner [0 ] 0
|
|
O_W Data_All_Tokens [45 ] 45
|
|
O_W Ack_Owner [0 ] 0
|
|
O_W Tokens [99 ] 99
|
|
O_W Ack_All_Tokens [7756 ] 7756
|
|
O_W Memory_Data [0 ] 0
|
|
O_W Memory_Ack [213410 ] 213410
|
|
O_W DMA_READ [0 ] 0
|
|
O_W DMA_WRITE [0 ] 0
|
|
O_W DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
L_O_W GETX [46215 ] 46215
|
|
L_O_W GETS [84470 ] 84470
|
|
L_O_W Lockdown [45 ] 45
|
|
L_O_W Unlockdown [0 ] 0
|
|
L_O_W Own_Lock_or_Unlock [0 ] 0
|
|
L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
L_O_W Data_Owner [0 ] 0
|
|
L_O_W Data_All_Tokens [0 ] 0
|
|
L_O_W Ack_Owner [0 ] 0
|
|
L_O_W Tokens [0 ] 0
|
|
L_O_W Ack_All_Tokens [88 ] 88
|
|
L_O_W Memory_Data [3490 ] 3490
|
|
L_O_W Memory_Ack [1635 ] 1635
|
|
L_O_W DMA_READ [0 ] 0
|
|
L_O_W DMA_WRITE [0 ] 0
|
|
L_O_W DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
L_NO_W GETX [42129 ] 42129
|
|
L_NO_W GETS [75055 ] 75055
|
|
L_NO_W Lockdown [898 ] 898
|
|
L_NO_W Unlockdown [0 ] 0
|
|
L_NO_W Own_Lock_or_Unlock [0 ] 0
|
|
L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
L_NO_W Data_Owner [0 ] 0
|
|
L_NO_W Data_All_Tokens [0 ] 0
|
|
L_NO_W Ack_Owner [0 ] 0
|
|
L_NO_W Tokens [0 ] 0
|
|
L_NO_W Ack_All_Tokens [12 ] 12
|
|
L_NO_W Memory_Data [191972 ] 191972
|
|
L_NO_W DMA_READ [0 ] 0
|
|
L_NO_W DMA_WRITE [0 ] 0
|
|
L_NO_W DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
DR_L_W GETX [0 ] 0
|
|
DR_L_W GETS [0 ] 0
|
|
DR_L_W Lockdown [0 ] 0
|
|
DR_L_W Unlockdown [0 ] 0
|
|
DR_L_W Own_Lock_or_Unlock [0 ] 0
|
|
DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
DR_L_W Data_Owner [0 ] 0
|
|
DR_L_W Data_All_Tokens [0 ] 0
|
|
DR_L_W Ack_Owner [0 ] 0
|
|
DR_L_W Tokens [0 ] 0
|
|
DR_L_W Ack_All_Tokens [0 ] 0
|
|
DR_L_W Request_Timeout [0 ] 0
|
|
DR_L_W Memory_Data [0 ] 0
|
|
DR_L_W DMA_READ [0 ] 0
|
|
DR_L_W DMA_WRITE [0 ] 0
|
|
DR_L_W DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
DW_L_W GETX [0 ] 0
|
|
DW_L_W GETS [0 ] 0
|
|
DW_L_W Lockdown [0 ] 0
|
|
DW_L_W Unlockdown [0 ] 0
|
|
DW_L_W Own_Lock_or_Unlock [0 ] 0
|
|
DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
DW_L_W Data_Owner [0 ] 0
|
|
DW_L_W Data_All_Tokens [0 ] 0
|
|
DW_L_W Ack_Owner [0 ] 0
|
|
DW_L_W Tokens [0 ] 0
|
|
DW_L_W Ack_All_Tokens [0 ] 0
|
|
DW_L_W Request_Timeout [0 ] 0
|
|
DW_L_W Memory_Ack [0 ] 0
|
|
DW_L_W DMA_READ [0 ] 0
|
|
DW_L_W DMA_WRITE [0 ] 0
|
|
DW_L_W DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
NO_W GETX [50776 ] 50776
|
|
NO_W GETS [89463 ] 89463
|
|
NO_W Lockdown [191977 ] 191977
|
|
NO_W Unlockdown [0 ] 0
|
|
NO_W Own_Lock_or_Unlock [0 ] 0
|
|
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
NO_W Data_Owner [0 ] 0
|
|
NO_W Data_All_Tokens [0 ] 0
|
|
NO_W Ack_Owner [0 ] 0
|
|
NO_W Tokens [0 ] 0
|
|
NO_W Ack_All_Tokens [0 ] 0
|
|
NO_W Memory_Data [413010 ] 413010
|
|
NO_W DMA_READ [0 ] 0
|
|
NO_W DMA_WRITE [0 ] 0
|
|
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
O_DW_W GETX [0 ] 0
|
|
O_DW_W GETS [0 ] 0
|
|
O_DW_W Lockdown [0 ] 0
|
|
O_DW_W Unlockdown [0 ] 0
|
|
O_DW_W Own_Lock_or_Unlock [0 ] 0
|
|
O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
O_DW_W Data_Owner [0 ] 0
|
|
O_DW_W Data_All_Tokens [0 ] 0
|
|
O_DW_W Ack_Owner [0 ] 0
|
|
O_DW_W Tokens [0 ] 0
|
|
O_DW_W Ack_All_Tokens [0 ] 0
|
|
O_DW_W Request_Timeout [0 ] 0
|
|
O_DW_W Memory_Ack [0 ] 0
|
|
O_DW_W DMA_READ [0 ] 0
|
|
O_DW_W DMA_WRITE [0 ] 0
|
|
O_DW_W DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
O_DR_W GETX [0 ] 0
|
|
O_DR_W GETS [0 ] 0
|
|
O_DR_W Lockdown [0 ] 0
|
|
O_DR_W Unlockdown [0 ] 0
|
|
O_DR_W Own_Lock_or_Unlock [0 ] 0
|
|
O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
O_DR_W Data_Owner [0 ] 0
|
|
O_DR_W Data_All_Tokens [0 ] 0
|
|
O_DR_W Ack_Owner [0 ] 0
|
|
O_DR_W Tokens [0 ] 0
|
|
O_DR_W Ack_All_Tokens [0 ] 0
|
|
O_DR_W Request_Timeout [0 ] 0
|
|
O_DR_W Memory_Data [0 ] 0
|
|
O_DR_W DMA_READ [0 ] 0
|
|
O_DR_W DMA_WRITE [0 ] 0
|
|
O_DR_W DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
O_DW GETX [0 ] 0
|
|
O_DW GETS [0 ] 0
|
|
O_DW Lockdown [0 ] 0
|
|
O_DW Unlockdown [0 ] 0
|
|
O_DW Own_Lock_or_Unlock [0 ] 0
|
|
O_DW Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
O_DW Data_Owner [0 ] 0
|
|
O_DW Data_All_Tokens [0 ] 0
|
|
O_DW Ack_Owner [0 ] 0
|
|
O_DW Ack_Owner_All_Tokens [0 ] 0
|
|
O_DW Tokens [0 ] 0
|
|
O_DW Ack_All_Tokens [0 ] 0
|
|
O_DW Request_Timeout [0 ] 0
|
|
O_DW DMA_READ [0 ] 0
|
|
O_DW DMA_WRITE [0 ] 0
|
|
O_DW DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
NO_DW GETX [0 ] 0
|
|
NO_DW GETS [0 ] 0
|
|
NO_DW Lockdown [0 ] 0
|
|
NO_DW Unlockdown [0 ] 0
|
|
NO_DW Own_Lock_or_Unlock [0 ] 0
|
|
NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
NO_DW Data_Owner [0 ] 0
|
|
NO_DW Data_All_Tokens [0 ] 0
|
|
NO_DW Tokens [0 ] 0
|
|
NO_DW Request_Timeout [0 ] 0
|
|
NO_DW DMA_READ [0 ] 0
|
|
NO_DW DMA_WRITE [0 ] 0
|
|
NO_DW DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
NO_DR GETX [0 ] 0
|
|
NO_DR GETS [0 ] 0
|
|
NO_DR Lockdown [0 ] 0
|
|
NO_DR Unlockdown [0 ] 0
|
|
NO_DR Own_Lock_or_Unlock [0 ] 0
|
|
NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
NO_DR Data_Owner [0 ] 0
|
|
NO_DR Data_All_Tokens [0 ] 0
|
|
NO_DR Tokens [0 ] 0
|
|
NO_DR Request_Timeout [0 ] 0
|
|
NO_DR DMA_READ [0 ] 0
|
|
NO_DR DMA_WRITE [0 ] 0
|
|
NO_DR DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
DW_L GETX [0 ] 0
|
|
DW_L GETS [0 ] 0
|
|
DW_L Lockdown [0 ] 0
|
|
DW_L Unlockdown [0 ] 0
|
|
DW_L Own_Lock_or_Unlock [0 ] 0
|
|
DW_L Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
DW_L Data_Owner [0 ] 0
|
|
DW_L Data_All_Tokens [0 ] 0
|
|
DW_L Ack_Owner [0 ] 0
|
|
DW_L Ack_Owner_All_Tokens [0 ] 0
|
|
DW_L Tokens [0 ] 0
|
|
DW_L Request_Timeout [0 ] 0
|
|
DW_L DMA_READ [0 ] 0
|
|
DW_L DMA_WRITE [0 ] 0
|
|
DW_L DMA_WRITE_All_Tokens [0 ] 0
|
|
|
|
DR_L GETX [0 ] 0
|
|
DR_L GETS [0 ] 0
|
|
DR_L Lockdown [0 ] 0
|
|
DR_L Unlockdown [0 ] 0
|
|
DR_L Own_Lock_or_Unlock [0 ] 0
|
|
DR_L Own_Lock_or_Unlock_Tokens [0 ] 0
|
|
DR_L Data_Owner [0 ] 0
|
|
DR_L Data_All_Tokens [0 ] 0
|
|
DR_L Ack_Owner [0 ] 0
|
|
DR_L Ack_Owner_All_Tokens [0 ] 0
|
|
DR_L Tokens [0 ] 0
|
|
DR_L Request_Timeout [0 ] 0
|
|
DR_L DMA_READ [0 ] 0
|
|
DR_L DMA_WRITE [0 ] 0
|
|
DR_L DMA_WRITE_All_Tokens [0 ] 0
|
|
|