sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
1939 commits 2 branches 0 tags 204 MiB
C++ 67.4%
Python 18.6%
C 11.5%
Assembly 1%
HTML 0.6%
Other 0.8%
Go to file
Nathan Binkert b7b8ffa7b7 Major changes to sinic device model. Rearrage read/write, better 
interrupts.

dev/sinic.cc:
    - The prepareRead function sets all the variables in the register
    file that depend on various state bits that change on the fly.
    Includes RxDone, RxWait, TxDone, and TxWait
    - Use the new register information accessor functions to grab
    validity and size information for the read and write functions
    - read all registers directly from the register space by offset
    and size, not by actual name (less code)
    - The side effect of reading the interrupt status (clearing it) now
    happens outside the actual chunk of code where the value is loaded.
    - Add an iprRead function for when we may want speculative access
    to device registers through an ipr or special instruction.
    - When RxData or TxData are written, their busy flag is set to
    indicate that they have an outstanding transaction.
    - The RxHigh and TxLow interrupts are special, they only interrupt
    if the rxEmpty or txFull limits were hit
    - Move reset to the command register
    - Update more registers on reset, clear rxEmpty and txFull
    - Data dumps only happen if EthernetData trace flag set
    - When a DMA completes, kick the other engine if it was waiting
    - implement all of the new interrupts
    - serialize the new stuff
dev/sinic.hh:
    - Put all registers with their proper size and alignment into
    the regs struct so that we can copy multiple at a time.
    - Provide accessor functions for accessing the registers with
    different sizes.
    - Flags to track when the rx fifo hit empty and the tx fifo became
    full.  These flags are used to determine what to do when below
    the watermarks, and are reset when crossing the watermark.
    - the txDmaEvent should actually trigger the txDmaDone function
    - Add an iprRead function for when we may want speculative access
    to device registers through an ipr or special instruction.
    - The prepareRead function sets all the variables in the register
    file that depend on various state bits that change on the fly.
    - add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
    Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
    rename XxThreshold to XxFifoMark
    Move Reset to the Command register
    Add Thread to the Config register
    New interrupts, better names
    More info in RxDone and TxDone
    Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
    Both sinic and nsgige have the dedicated thread
    Add a parameter to configure the maximum number for receive
    packets per interrupt

--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-21 20:28:21 -04:00
arch Minor tweak to isa_parser. 2005-10-20 14:14:59 -04:00
base Add new function profiling stuff, wrap the pc_sample stuff into it. 2005-10-18 19:07:42 -04:00
build Add default= option to SConstruct. 2005-10-01 11:32:33 -04:00
configs various changes to the boot scripts 2005-09-16 22:54:01 -04:00
cpu Add new function profiling stuff, wrap the pc_sample stuff into it. 2005-10-18 19:07:42 -04:00
dev Major changes to sinic device model. Rearrage read/write, better 2005-10-21 20:28:21 -04:00
docs Many files: 2005-06-05 05:16:00 -04:00
encumbered/cpu/full Many files: 2005-06-05 05:16:00 -04:00
kern Add new function profiling stuff, wrap the pc_sample stuff into it. 2005-10-18 19:07:42 -04:00
python Major changes to sinic device model. Rearrage read/write, better 2005-10-21 20:28:21 -04:00
sim Add new function profiling stuff, wrap the pc_sample stuff into it. 2005-10-18 19:07:42 -04:00
test fix nmtest 2005-10-18 19:18:27 -04:00
util Fix a couple of bug in the values() vector accessor 2005-10-21 17:28:47 -04:00
Doxyfile Fix minor doxygen issues. 2005-06-05 08:08:29 -04:00
LICENSE Fix a few broken or inconsistently formatted copyrights 2005-06-05 05:08:37 -04:00
README More documentation for 1.1 release. 2005-10-06 13:59:05 -04:00
RELEASE_NOTES More documentation for 1.1 release. 2005-10-06 13:59:05 -04:00
SConscript Add new function profiling stuff, wrap the pc_sample stuff into it. 2005-10-18 19:07:42 -04:00

README 

This is release m5_1.1 of the M5 simulator.

This file contains brief "getting started" instructions.  For more
information, see http://m5.eecs.umich.edu.  If you have questions,
please send mail to m5sim-users@lists.sourceforge.net.

WHAT'S INCLUDED (AND NOT)
-------------------------

The basic source release includes these subdirectories:
 - m5: the simulator itself
 - m5-test: regression tests
 - ext: less-common external packages needed to build m5
 - alpha-system: source for Alpha console and PALcode

To run full-system simulations, you will need compiled console,
PALcode, and kernel binaries and one or more disk images.  These files
are collected in a separate archive, m5_system_1.1.tar.bz2.  This file
is included on the CD release, or you can download it separately from
Sourceforge.

M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP
Tru64 version of Unix. We are able to distribute Linux and FreeBSD
bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-dev@eecs.umich.edu.

The CD release includes a few extra goodies, such as a tar file
containing doxygen-generated HTML documentation (html-docs.tar.gz), a
set of Linux source patches (linux_m5-2.6.8.1.diff), and the scons
program needed to build M5.  If you do not have the CD, the same HTML
documentation is available online at http://m5.eecs.umich.edu/docs,
the Linux source patches are available at
http://m5.eecs.umich.edu/dist/linux_m5-2.6.8.1.diff, and the scons
program is available from http://www.scons.org.

WHAT'S NEEDED
-------------
- GCC version 3.3 or newer
- Python 2.3 or newer
- SCons 0.96.1 or newer (see http://www.scons.org)

WHAT'S RECOMMENDED
------------------
- MySQL (for statistics complex statistics storage/retrieval)
- Python-MysqlDB (for statistics analysis) 

GETTING STARTED
---------------

There are two different build targets and three optimizations levels:

Target:
-------
ALPHA_SE - Syscall emulation simulation
ALPHA_FS - Full system simulation

Optimization:
-------------
m5.debug - debug version of the code with tracing and without optimization
m5.opt   - optimized version of code with tracing
m5.fast  - optimized version of the code without tracing and asserts

Different targets are built in different subdirectories of m5/build.
Binaries with the same target but different optimization levels share
the same directory.  Note that you can build m5 in any directory you
choose;p just configure the target directory using the 'mkbuilddir'
script in m5/build.

The following steps will build and test the simulator.  The variable
"$top" refers to the top directory where you've unpacked the files,
i.e., the one containing the m5, m5-test, and ext directories.  If you
have a multiprocessor system, you should give scons a "-j N" argument (like
make) to run N jobs in parallel.

To build and test the syscall-emulation simulator:

	cd $top/m5/build
	scons ALPHA_SE/test/opt/quick

This process takes under 10 minutes on a dual 3GHz Xeon system (using
the '-j 4' option).

To build and test the full-system simulator:

1. Unpack the full-system binaries from m5_system_1.1.tar.bz2.  (See
   above for directions on obtaining this file if you don't have it.)
   This package includes disk images and kernel, palcode, and console
   binaries for Linux and FreeBSD.
2. Edit the SYSTEMDIR search path in $top/m5-test/SysPaths.py to
   include the path to your local copy of the binaries.
3. In $top/m5/build, run "scons ALPHA_FS/test/opt/quick".

This process also takes under 10 minutes on a dual 3GHz Xeon system
(again using the '-j 4' option).