79613686f0
minor change to syntax of 'def operands' in ISA descriptions.
arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
Change 'def operands' statement to work with new
isa_parser changes.
arch/isa_parser.py:
Merge OperandTraits and OperandDescriptor objects into a
unified hierarchy of Operand objects.
Required a change in the syntax of the 'def operands'
statement in the ISA description.
--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
33 lines
1.2 KiB
Plaintext
33 lines
1.2 KiB
Plaintext
def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'shw' : ('signed int', 16),
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'uhw' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'sdw' : ('signed int', 64),
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'udw' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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'qf' : ('float', 128)
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}};
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def operands {{
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# Int regs default to unsigned, but code should not count on this.
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# For clarity, descriptions that depend on unsigned behavior should
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# explicitly specify '.uq'.
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'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
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'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2),
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'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3),
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#'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
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#'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
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#'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
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'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
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#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
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#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
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#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
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# The next two are hacks for non-full-system call-pal emulation
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#'R0': ('IntReg', 'uq', '0', None, 1),
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#'R16': ('IntReg', 'uq', '16', None, 1)
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}};
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