1f6d5f8f84
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh
194 lines
6.8 KiB
Python
194 lines
6.8 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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addToPath('../common')
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addToPath('../ruby')
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addToPath('../topologies')
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import Options
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import Ruby
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# Get paths we might need. It's expected this file is in m5/configs/example.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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parser.add_option("--maxloads", metavar="N", default=0,
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help="Stop after N loads")
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parser.add_option("--progress", type="int", default=1000,
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metavar="NLOADS",
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help="Progress message interval "
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"[default: %default]")
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parser.add_option("--num-dmas", type="int", default=0, help="# of dma testers")
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parser.add_option("--functional", type="int", default=0,
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help="percentage of accesses that should be functional")
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parser.add_option("--suppress-func-warnings", action="store_true",
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help="suppress warnings when functional accesses fail")
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#
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# Add the ruby specific and protocol specific options
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#
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Ruby.define_options(parser)
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execfile(os.path.join(config_root, "common", "Options.py"))
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(options, args) = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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options.l1d_size="256B"
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options.l1i_size="256B"
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options.l2_size="512B"
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options.l3_size="1kB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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block_size = 64
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if options.num_cpus > block_size:
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print "Error: Number of testers %d limited to %d because of false sharing" \
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% (options.num_cpus, block_size)
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sys.exit(1)
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#
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# Currently ruby does not support atomic or uncacheable accesses
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#
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cpus = [ MemTest(atomic = False,
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max_loads = options.maxloads,
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issue_dmas = False,
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percent_functional = options.functional,
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percent_uncacheable = 0,
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progress_interval = options.progress,
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suppress_func_warnings = options.suppress_func_warnings) \
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for i in xrange(options.num_cpus) ]
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system = System(cpu = cpus,
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funcmem = SimpleMemory(in_addr_map = False),
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funcbus = NoncoherentXBar(),
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physmem = SimpleMemory(),
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clk_domain = SrcClockDomain(clock = options.sys_clock),
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mem_ranges = [AddrRange(options.mem_size)])
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if options.num_dmas > 0:
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dmas = [ MemTest(atomic = False,
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max_loads = options.maxloads,
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issue_dmas = True,
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percent_functional = 0,
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percent_uncacheable = 0,
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progress_interval = options.progress,
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suppress_func_warnings =
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not options.suppress_func_warnings) \
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for i in xrange(options.num_dmas) ]
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system.dma_devices = dmas
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else:
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dmas = []
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dma_ports = []
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for (i, dma) in enumerate(dmas):
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dma_ports.append(dma.test)
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Ruby.create_system(options, system, dma_ports = dma_ports)
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# Create a top-level voltage domain and clock domain
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system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = system.voltage_domain)
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# Create a seperate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = system.voltage_domain)
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#
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# The tester is most effective when randomization is turned on and
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# artifical delay is randomly inserted on messages
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#
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system.ruby.randomization = True
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assert(len(cpus) == len(system.ruby._cpu_ports))
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for (i, cpu) in enumerate(cpus):
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#
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# Tie the cpu memtester ports to the correct system ports
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#
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cpu.test = system.ruby._cpu_ports[i].slave
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cpu.functional = system.funcbus.slave
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#
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# Since the memtester is incredibly bursty, increase the deadlock
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# threshold to 5 million cycles
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#
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system.ruby._cpu_ports[i].deadlock_threshold = 5000000
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#
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# Ruby doesn't need the backing image of memory when running with
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# the tester.
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#
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system.ruby._cpu_ports[i].access_phys_mem = False
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for (i, dma) in enumerate(dmas):
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#
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# Tie the dma memtester ports to the correct functional port
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# Note that the test port has already been connected to the dma_sequencer
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#
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dma.functional = system.funcbus.slave
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# connect reference memory to funcbus
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system.funcbus.master = system.funcmem.port
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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# instantiate configuration
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m5.instantiate()
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# simulate until program terminates
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exit_event = m5.simulate(options.abs_max_tick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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