0deef376d9
This patch includes software engineering changes and some generic bug fixes
Joel Hestness and Yasuko Eckert made to McPAT 0.8. There are still known
issues/concernts we did not have a chance to address in this patch.
High-level changes in this patch include:
1) Making XML parsing modular and hierarchical:
- Shift parsing responsibility into the components
- Read XML in a (mostly) context-free recursive manner so that McPAT input
files can contain arbitrary component hierarchies
2) Making power, energy, and area calculations a hierarchical and recursive
process
- Components track their subcomponents and recursively call compute
functions in stages
- Make C++ object hierarchy reflect inheritance of classes of components
with similar structures
- Simplify computeArea() and computeEnergy() functions to eliminate
successive calls to calculate separate TDP vs. runtime energy
- Remove Processor component (now unnecessary) and introduce a more abstract
System component
3) Standardizing McPAT output across all components
- Use a single, common data structure for storing and printing McPAT output
- Recursively call print functions through component hierarchy
4) For caches, allow splitting data array and tag array reads and writes for
better accuracy
5) Improving the usability of CACTI by printing more helpful warning and error
messages
6) Minor: Impose more rigorous code style for clarity (more work still to be
done)
Overall, these changes greatly reduce the amount of replicated code, and they
improve McPAT runtime and decrease memory footprint.
359 lines
10 KiB
C++
359 lines
10 KiB
C++
/*****************************************************************************
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* McPAT/CACTI
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2012 Hewlett-Packard Development Company, L.P.
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* Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#ifndef __PARAMETER_H__
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#define __PARAMETER_H__
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#include "area.h"
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#include "cacti_interface.h"
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#include "const.h"
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#include "io.h"
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// parameters which are functions of certain device technology
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class TechnologyParameter {
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public:
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class DeviceType {
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public:
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double C_g_ideal;
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double C_fringe;
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double C_overlap;
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double C_junc; // C_junc_area
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double C_junc_sidewall;
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double l_phy;
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double l_elec;
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double R_nch_on;
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double R_pch_on;
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double Vdd;
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double Vth;
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double I_on_n;
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double I_on_p;
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double I_off_n;
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double I_off_p;
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double I_g_on_n;
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double I_g_on_p;
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double C_ox;
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double t_ox;
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double n_to_p_eff_curr_drv_ratio;
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double long_channel_leakage_reduction;
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DeviceType(): C_g_ideal(0), C_fringe(0), C_overlap(0), C_junc(0),
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C_junc_sidewall(0), l_phy(0), l_elec(0), R_nch_on(0), R_pch_on(0),
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Vdd(0), Vth(0),
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I_on_n(0), I_on_p(0), I_off_n(0), I_off_p(0), I_g_on_n(0),
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I_g_on_p(0),
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C_ox(0), t_ox(0), n_to_p_eff_curr_drv_ratio(0),
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long_channel_leakage_reduction(0) { };
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void reset() {
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C_g_ideal = 0;
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C_fringe = 0;
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C_overlap = 0;
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C_junc = 0;
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l_phy = 0;
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l_elec = 0;
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R_nch_on = 0;
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R_pch_on = 0;
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Vdd = 0;
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Vth = 0;
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I_on_n = 0;
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I_on_p = 0;
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I_off_n = 0;
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I_off_p = 0;
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I_g_on_n = 0;
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I_g_on_p = 0;
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C_ox = 0;
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t_ox = 0;
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n_to_p_eff_curr_drv_ratio = 0;
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long_channel_leakage_reduction = 0;
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}
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void display(uint32_t indent = 0);
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};
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class InterconnectType {
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public:
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double pitch;
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double R_per_um;
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double C_per_um;
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double horiz_dielectric_constant;
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double vert_dielectric_constant;
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double aspect_ratio;
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double miller_value;
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double ild_thickness;
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InterconnectType(): pitch(0), R_per_um(0), C_per_um(0) { };
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void reset() {
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pitch = 0;
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R_per_um = 0;
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C_per_um = 0;
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horiz_dielectric_constant = 0;
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vert_dielectric_constant = 0;
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aspect_ratio = 0;
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miller_value = 0;
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ild_thickness = 0;
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}
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void display(uint32_t indent = 0);
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};
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class MemoryType {
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public:
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double b_w;
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double b_h;
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double cell_a_w;
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double cell_pmos_w;
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double cell_nmos_w;
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double Vbitpre;
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void reset() {
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b_w = 0;
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b_h = 0;
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cell_a_w = 0;
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cell_pmos_w = 0;
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cell_nmos_w = 0;
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Vbitpre = 0;
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}
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void display(uint32_t indent = 0);
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};
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class ScalingFactor {
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public:
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double logic_scaling_co_eff;
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double core_tx_density;
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double long_channel_leakage_reduction;
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ScalingFactor(): logic_scaling_co_eff(0), core_tx_density(0),
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long_channel_leakage_reduction(0) { };
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void reset() {
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logic_scaling_co_eff = 0;
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core_tx_density = 0;
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long_channel_leakage_reduction = 0;
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}
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void display(uint32_t indent = 0);
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};
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double ram_wl_stitching_overhead_;
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double min_w_nmos_;
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double max_w_nmos_;
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double max_w_nmos_dec;
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double unit_len_wire_del;
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double FO4;
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double kinv;
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double vpp;
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double w_sense_en;
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double w_sense_n;
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double w_sense_p;
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double sense_delay;
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double sense_dy_power;
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double w_iso;
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double w_poly_contact;
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double spacing_poly_to_poly;
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double spacing_poly_to_contact;
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double w_comp_inv_p1;
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double w_comp_inv_p2;
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double w_comp_inv_p3;
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double w_comp_inv_n1;
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double w_comp_inv_n2;
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double w_comp_inv_n3;
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double w_eval_inv_p;
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double w_eval_inv_n;
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double w_comp_n;
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double w_comp_p;
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double dram_cell_I_on;
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double dram_cell_Vdd;
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double dram_cell_I_off_worst_case_len_temp;
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double dram_cell_C;
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double gm_sense_amp_latch;
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double w_nmos_b_mux;
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double w_nmos_sa_mux;
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double w_pmos_bl_precharge;
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double w_pmos_bl_eq;
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double MIN_GAP_BET_P_AND_N_DIFFS;
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double MIN_GAP_BET_SAME_TYPE_DIFFS;
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double HPOWERRAIL;
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double cell_h_def;
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double chip_layout_overhead;
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double macro_layout_overhead;
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double sckt_co_eff;
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double fringe_cap;
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uint64_t h_dec;
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DeviceType sram_cell; // SRAM cell transistor
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DeviceType dram_acc; // DRAM access transistor
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DeviceType dram_wl; // DRAM wordline transistor
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DeviceType peri_global; // peripheral global
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DeviceType cam_cell; // SRAM cell transistor
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InterconnectType wire_local;
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InterconnectType wire_inside_mat;
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InterconnectType wire_outside_mat;
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ScalingFactor scaling_factor;
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MemoryType sram;
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MemoryType dram;
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MemoryType cam;
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void display(uint32_t indent = 0);
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void reset() {
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dram_cell_Vdd = 0;
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dram_cell_I_on = 0;
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dram_cell_C = 0;
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vpp = 0;
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sense_delay = 0;
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sense_dy_power = 0;
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fringe_cap = 0;
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// horiz_dielectric_constant = 0;
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// vert_dielectric_constant = 0;
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// aspect_ratio = 0;
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// miller_value = 0;
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// ild_thickness = 0;
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dram_cell_I_off_worst_case_len_temp = 0;
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sram_cell.reset();
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dram_acc.reset();
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dram_wl.reset();
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peri_global.reset();
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cam_cell.reset();
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scaling_factor.reset();
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wire_local.reset();
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wire_inside_mat.reset();
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wire_outside_mat.reset();
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sram.reset();
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dram.reset();
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cam.reset();
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chip_layout_overhead = 0;
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macro_layout_overhead = 0;
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sckt_co_eff = 0;
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}
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};
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class DynamicParameter {
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public:
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bool is_tag;
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bool pure_ram;
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bool pure_cam;
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bool fully_assoc;
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int tagbits;
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int num_subarrays; // only for leakage computation -- the number of subarrays per bank
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int num_mats; // only for leakage computation -- the number of mats per bank
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double Nspd;
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int Ndwl;
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int Ndbl;
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int Ndcm;
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int deg_bl_muxing;
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int deg_senseamp_muxing_non_associativity;
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int Ndsam_lev_1;
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int Ndsam_lev_2;
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int number_addr_bits_mat; // per port
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int number_subbanks_decode; // per_port
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int num_di_b_bank_per_port;
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int num_do_b_bank_per_port;
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int num_di_b_mat;
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int num_do_b_mat;
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int num_di_b_subbank;
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int num_do_b_subbank;
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int num_si_b_mat;
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int num_so_b_mat;
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int num_si_b_subbank;
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int num_so_b_subbank;
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int num_si_b_bank_per_port;
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int num_so_b_bank_per_port;
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int number_way_select_signals_mat;
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int num_act_mats_hor_dir;
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int num_act_mats_hor_dir_sl;
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bool is_dram;
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double V_b_sense;
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unsigned int num_r_subarray;
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unsigned int num_c_subarray;
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int tag_num_r_subarray;//sheng: fully associative cache tag and data must be computed together, data and tag must be separate
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int tag_num_c_subarray;
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int data_num_r_subarray;
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int data_num_c_subarray;
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int num_mats_h_dir;
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int num_mats_v_dir;
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uint32_t ram_cell_tech_type;
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double dram_refresh_period;
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DynamicParameter();
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DynamicParameter(
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bool is_tag_,
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int pure_ram_,
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int pure_cam_,
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double Nspd_,
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unsigned int Ndwl_,
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unsigned int Ndbl_,
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unsigned int Ndcm_,
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unsigned int Ndsam_lev_1_,
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unsigned int Ndsam_lev_2_,
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bool is_main_mem_);
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int use_inp_params;
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unsigned int num_rw_ports;
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unsigned int num_rd_ports;
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unsigned int num_wr_ports;
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unsigned int num_se_rd_ports; // number of single ended read ports
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unsigned int num_search_ports;
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unsigned int out_w;// == nr_bits_out
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bool is_main_mem;
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Area cell, cam_cell;//cell is the sram_cell in both nomal cache/ram and FA.
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bool is_valid;
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};
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extern InputParameter * g_ip;
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extern TechnologyParameter g_tp;
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#endif
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