c1aecc05e6
This patch extensively modifies DSENT so that it can be accessed using Python. To access the Python interface, DSENT needs to compiled as a shared library. For this purpose a CMakeLists.txt file has been added. Some of the code that is not required is being removed.
188 lines
7.1 KiB
Text
188 lines
7.1 KiB
Text
# Copyright (c) 2012 Massachusetts Institute of Technology
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# WARNING: Most commercial fabs will not be happy if you release their exact
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# process information! If you derive these numbers through SPICE models,
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# the process design kit, or any other confidential material, please round-off
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# the values and leave the process name unidentifiable by fab (i.e. call it
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# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
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# rule may not apply for open processes, but you may want to check.
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# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
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# This file contains the model for a bulk 45nm LVT process
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Name = Bulk45LVT
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# Supply voltage used in the circuit and for characterizations (V)
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Vdd = 1.0
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# Temperature (K)
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Temperature = 340
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# =============================================================================
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# Parameters for transistors
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# =============================================================================
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# Contacted gate pitch (m)
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Gate->PitchContacted = 0.200e-6
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# Min gate width (m)
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Gate->MinWidth = 0.160e-6
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# Gate cap per unit width (F/m)
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Gate->CapPerWidth = 1.000e-9
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# Source/Drain cap per unit width (F/m)
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Drain->CapPerWidth = 0.600e-9
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# Parameters characterization temperature (K)
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Nmos->CharacterizedTemperature = 300.0
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Pmos->CharacterizedTemperature = 300.0
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#------------------------------------------------------------------------------
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# I_Eff definition in Na, IEDM 2002
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# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
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# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
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# This is generally accurate for when input and output transition times
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# are similar, which is a reasonable case after timing optimization
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#------------------------------------------------------------------------------
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# Effective resistance (Ohm-m)
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Nmos->EffResWidth = 1.100e-3
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Pmos->EffResWidth = 1.500e-3
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#------------------------------------------------------------------------------
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# The ratio of extra effective resistance with each additional stacked
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# transistor
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# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
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# For example, inverter has an normalized effective drive resistance of 1.0.
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# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
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# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
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# works relatively well up to 4 stacks. This value will change depending on the
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# VDD used.
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#------------------------------------------------------------------------------
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# Effective resistance stack ratio
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Nmos->EffResStackRatio = 0.7
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Pmos->EffResStackRatio = 0.6
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#------------------------------------------------------------------------------
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# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
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# Minimum off current is used as a second fit point, since I_OFF often
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# stops scaling with transistor width below some threshold
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#------------------------------------------------------------------------------
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# Off current per width (A/m)
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Nmos->OffCurrent = 100e-3
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Pmos->OffCurrent = 100e-3
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# Minimum off current (A)
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Nmos->MinOffCurrent = 100e-9
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Pmos->MinOffCurrent = 20e-9
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# Subthreshold swing (V/dec)
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Nmos->SubthresholdSwing = 0.100
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Pmos->SubthresholdSwing = 0.100
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# DIBL factor (V/V)
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Nmos->DIBL = 0.150
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Pmos->DIBL = 0.150
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# Subthreshold leakage temperature swing (K/dec)
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Nmos->SubthresholdTempSwing = 100
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Pmos->SubthresholdTempSwing = 100
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#------------------------------------------------------------------------------
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# =============================================================================
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# Parameters for interconnect
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# =============================================================================
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Wire->AvailableLayers = [Metal1,Local,Intermediate,Global]
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# Metal 1 Wire (used for std cell routing only)
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# Min width (m)
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Wire->Metal1->MinWidth = 80e-9
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# Min spacing (m)
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Wire->Metal1->MinSpacing = 80e-9
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# Resistivity (Ohm-m)
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Wire->Metal1->Resistivity = 3.00e-8
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# Metal thickness (m)
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Wire->Metal1->MetalThickness = 140.0e-9
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# Dielectric thickness (m)
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Wire->Metal1->DielectricThickness = 130.0e-9
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# Dielectric constant
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Wire->Metal1->DielectricConstant = 3.2
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# Local wire, 1.0X of the M1 pitch
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# Min width (m)
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Wire->Metal1->MinWidth = 80e-9
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# Min spacing (m)
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Wire->Metal1->MinSpacing = 80e-9
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# Resistivity (Ohm-m)
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Wire->Metal1->Resistivity = 3.00e-8
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# Metal thickness (m)
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Wire->Metal1->MetalThickness = 140.0e-9
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# Dielectric thickness (m)
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Wire->Metal1->DielectricThickness = 130.0e-9
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# Dielectric constant
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Wire->Metal1->DielectricConstant = 3.2
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# Intermediate wire, 1.4X the M1 pitch
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# Min width (m)
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Wire->Intermediate->MinWidth = 110e-9
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# Min spacing (m)
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Wire->Intermediate->MinSpacing = 110e-9
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# Resistivity (Ohm-m)
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Wire->Intermediate->Resistivity = 2.60e-8
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# Metal thickness (m)
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Wire->Intermediate->MetalThickness = 200e-9
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# Dielectric thickness (m)
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Wire->Intermediate->DielectricThickness = 170e-9
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# Dielectric constant
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Wire->Intermediate->DielectricConstant = 3.00
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# Global wire, 2.0X the M1 pitch
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# Min width (m)
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Wire->Global->MinWidth = 160e-9
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# Min spacing (m)
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Wire->Global->MinSpacing = 160e-9
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# Resistivity (Ohm-m)
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Wire->Global->Resistivity = 2.30e-8
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# Metal thickness (m)
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Wire->Global->MetalThickness = 280e-9
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# Dielectric thickness (m)
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Wire->Global->DielectricThickness = 250e-9
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# Dielectric constant
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Wire->Global->DielectricConstant = 2.80
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# =============================================================================
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# Parameters for Standard Cells
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# =============================================================================
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# The height of the standard cell is usually a multiple of the vertical
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# M1 pitch (tracks). By definition, an X1 size cell has transistors
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# that fit exactly in the given cell height without folding, or leaving
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# any wasted vertical area
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# Reasonable values for the number of M1 tracks that we have seen are 8-14
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StdCell->Tracks = 11
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# Height overhead due to supply rails, well spacing, etc. Note that this will grow
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# if the height of the standard cell decreases!
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StdCell->HeightOverheadFactor = 1.400
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# Sets the available sizes of each standard cell. Keep in mind that
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# 1.0 is the biggest cell without any transistor folding
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StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
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