77b9829f13
base/timebuf.hh:
Updated copyright.
cpu/o3/2bit_local_pred.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/btb.hh:
cpu/o3/comm.hh:
cpu/o3/commit.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/cpu_policy.hh:
cpu/o3/decode.hh:
cpu/o3/fetch.hh:
cpu/o3/free_list.hh:
cpu/o3/iew.hh:
cpu/o3/inst_queue.hh:
cpu/o3/mem_dep_unit.hh:
cpu/o3/ras.hh:
cpu/o3/regfile.hh:
cpu/o3/rename.hh:
cpu/o3/rename_map.hh:
cpu/o3/rob.cc:
cpu/o3/rob.hh:
cpu/o3/rob_impl.hh:
cpu/o3/sat_counter.hh:
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Updated #define to have correct path.
docs/footer.html:
Remove e-mail addr.
--HG--
extra : convert_revision : 68d7af52674621dc3b6d6ac0d564790ffd595fe3
82 lines
3 KiB
C++
82 lines
3 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_CPU_ALPHA_IMPL_HH__
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#define __CPU_O3_CPU_ALPHA_IMPL_HH__
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#include "arch/alpha/isa_traits.hh"
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#include "cpu/o3/alpha_params.hh"
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#include "cpu/o3/cpu_policy.hh"
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// Forward declarations.
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template <class Impl>
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class AlphaDynInst;
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template <class Impl>
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class AlphaFullCPU;
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/** Implementation specific struct that defines several key things to the
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* CPU, the stages within the CPU, the time buffers, and the DynInst.
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* The struct defines the ISA, the CPU policy, the specific DynInst, the
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* specific FullCPU, and all of the structs from the time buffers to do
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* communication.
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* This is one of the key things that must be defined for each hardware
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* specific CPU implementation.
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*/
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struct AlphaSimpleImpl
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{
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/** The ISA to be used. */
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typedef AlphaISA ISA;
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/** The type of MachInst. */
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typedef ISA::MachInst MachInst;
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/** The CPU policy to be used (ie fetch, decode, etc.). */
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typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
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/** The DynInst to be used. */
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typedef AlphaDynInst<AlphaSimpleImpl> DynInst;
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/** The refcounted DynInst pointer to be used. In most cases this is
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* what should be used, and not DynInst *.
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*/
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typedef RefCountingPtr<DynInst> DynInstPtr;
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/** The FullCPU to be used. */
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typedef AlphaFullCPU<AlphaSimpleImpl> FullCPU;
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/** The Params to be passed to each stage. */
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typedef AlphaSimpleParams Params;
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enum {
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MaxWidth = 8
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};
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};
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#endif // __CPU_O3_CPU_ALPHA_IMPL_HH__
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