5fb00e1df6
This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
22 lines
1 KiB
Text
Executable file
22 lines
1 KiB
Text
Executable file
warn: Sockets disabled, not accepting vnc client connections
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warn: Sockets disabled, not accepting terminal connections
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warn: Sockets disabled, not accepting gdb connections
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warn: The clidr register always reports 0 caches.
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warn: clidr LoUIS field of 0b001 to match current ARM implementations.
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warn: The csselr register isn't implemented.
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warn: The ccsidr register isn't implemented and always reads as 0.
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warn: instruction 'mcr bpiallis' unimplemented
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warn: instruction 'mcr icialluis' unimplemented
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warn: instruction 'mcr dccimvac' unimplemented
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warn: instruction 'mcr dccmvau' unimplemented
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warn: instruction 'mcr icimvau' unimplemented
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hack: be nice to actually delete the event here
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warn: LCD dual screen mode not supported
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warn: instruction 'mcr icialluis' unimplemented
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warn: instruction 'mcr bpiallis' unimplemented
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warn: User mode does not have SPSR
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warn: User mode does not have SPSR
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warn: User mode does not have SPSR
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warn: User mode does not have SPSR
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warn: User mode does not have SPSR
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warn: User mode does not have SPSR
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