737 lines
80 KiB
Plaintext
737 lines
80 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 691 # Number of BTB hits
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global.BPredUnit.BTBLookups 3468 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 112 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 1111 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 2334 # Number of conditional branches predicted
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global.BPredUnit.lookups 4040 # Number of BP lookups
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global.BPredUnit.usedRAS 559 # Number of times the RAS was used to get a target.
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host_inst_rate 99825 # Simulator instruction rate (inst/s)
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host_mem_usage 197616 # Number of bytes of host memory used
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host_seconds 0.11 # Real time elapsed on the host
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host_tick_rate 48783081 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads.
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memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 44 # Number of conflicting stores.
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memdepunit.memDep.conflictingStores 38 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 1952 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedLoads 1960 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 1112 # Number of stores inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 1121 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 11247 # Number of instructions simulated
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sim_seconds 0.000006 # Number of seconds simulated
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sim_ticks 5506000 # Number of ticks simulated
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system.cpu.commit.COM:branches 1724 # Number of branches committed
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system.cpu.commit.COM:branches_0 862 # Number of branches committed
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system.cpu.commit.COM:branches_1 862 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 153 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 10938
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 6318 5776.19%
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1 2129 1946.43%
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2 954 872.19%
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3 501 458.04%
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4 328 299.87%
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5 233 213.02%
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6 214 195.65%
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7 108 98.74%
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8 153 139.88%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 11281 # Number of instructions committed
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system.cpu.commit.COM:count_0 5641 # Number of instructions committed
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system.cpu.commit.COM:count_1 5640 # Number of instructions committed
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system.cpu.commit.COM:loads 1958 # Number of loads committed
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system.cpu.commit.COM:loads_0 979 # Number of loads committed
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system.cpu.commit.COM:loads_1 979 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed
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system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 3582 # Number of memory references committed
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system.cpu.commit.COM:refs_0 1791 # Number of memory references committed
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system.cpu.commit.COM:refs_1 1791 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
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system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 859 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 8029 # The number of squashed insts skipped by commit
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system.cpu.committedInsts_0 5624 # Number of Instructions Simulated
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system.cpu.committedInsts_1 5623 # Number of Instructions Simulated
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system.cpu.committedInsts_total 11247 # Number of Instructions Simulated
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system.cpu.cpi_0 1.952703 # CPI: Cycles Per Instruction
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system.cpu.cpi_1 1.953050 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.976438 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 2963 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses_0 2963 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency_0 12228.855721 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 7833.333333 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 2762 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits_0 2762 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 2458000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency_0 2458000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate_0 0.067837 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 201 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses_0 201 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_hits_0 75 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1574500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency_0 1574500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067837 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 201 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses_0 201 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 1252 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses_0 1252 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency_0 21841.954023 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 6695.402299 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 1078 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits_0 1078 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 3800500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency_0 3800500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate_0 0.138978 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 174 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses_0 174 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 372 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits_0 372 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 1165000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency_0 1165000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.138978 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 11.146974 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 4215 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses_0 4215 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency_0 16689.333333 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency_0 7305.333333 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
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system.cpu.dcache.demand_hits 3840 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits_0 3840 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 6258500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency_0 6258500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate_0 0.088968 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
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system.cpu.dcache.demand_misses 375 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses_0 375 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 447 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits_0 447 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 2739500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency_0 2739500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate_0 0.088968 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 375 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses_0 375 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated
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system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 4215 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses_0 4215 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency_0 16689.333333 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency_0 7305.333333 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 3840 # number of overall hits
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system.cpu.dcache.overall_hits_0 3840 # number of overall hits
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system.cpu.dcache.overall_hits_1 0 # number of overall hits
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system.cpu.dcache.overall_miss_latency 6258500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency_0 6258500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate_0 0.088968 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
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system.cpu.dcache.overall_misses 375 # number of overall misses
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system.cpu.dcache.overall_misses_0 375 # number of overall misses
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system.cpu.dcache.overall_misses_1 0 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 447 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits_0 447 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 2739500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency_0 2739500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate_0 0.088968 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 375 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses_0 375 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.replacements_0 0 # number of replacements
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system.cpu.dcache.replacements_1 0 # number of replacements
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system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 219.667658 # Cycle average of tags in use
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system.cpu.dcache.total_refs 3868 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dcache.writebacks_0 0 # number of writebacks
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system.cpu.dcache.writebacks_1 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 1907 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 262 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 358 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 22173 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 14421 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 3707 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 1515 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 340 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 183 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 4040 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 2997 # Number of cache lines fetched
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system.cpu.fetch.Cycles 7042 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 24368 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 1175 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.367875 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 2997 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 1250 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 2.218904 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 10982
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system.cpu.fetch.rateDist.min_value 0
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0 6938 6317.61%
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1 305 277.73%
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2 235 213.99%
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3 261 237.66%
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4 343 312.33%
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5 297 270.44%
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6 304 276.82%
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7 263 239.48%
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8 2036 1853.94%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 2933 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses_0 2933 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency_0 8509.630819 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 6073.033708 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 2310 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits_0 2310 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 5301500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency_0 5301500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate_0 0.212411 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 623 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses_0 623 # number of ReadReq misses
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|
system.cpu.icache.ReadReq_mshr_hits 64 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits_0 64 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 3783500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency_0 3783500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate_0 0.212411 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_misses 623 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses_0 623 # number of ReadReq MSHR misses
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_refs 3.707865 # Average number of references to valid blocks.
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.demand_accesses 2933 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses_0 2933 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency_0 8509.630819 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency_0 6073.033708 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
|
|
system.cpu.icache.demand_hits 2310 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits_0 2310 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_miss_latency 5301500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency_0 5301500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate_0 0.212411 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
|
|
system.cpu.icache.demand_misses 623 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses_0 623 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits_0 64 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_miss_latency 3783500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency_0 3783500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate_0 0.212411 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_misses 623 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses_0 623 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.overall_accesses 2933 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses_0 2933 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency_0 8509.630819 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency_0 6073.033708 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_hits 2310 # number of overall hits
|
|
system.cpu.icache.overall_hits_0 2310 # number of overall hits
|
|
system.cpu.icache.overall_hits_1 0 # number of overall hits
|
|
system.cpu.icache.overall_miss_latency 5301500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency_0 5301500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate_0 0.212411 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
|
|
system.cpu.icache.overall_misses 623 # number of overall misses
|
|
system.cpu.icache.overall_misses_0 623 # number of overall misses
|
|
system.cpu.icache.overall_misses_1 0 # number of overall misses
|
|
system.cpu.icache.overall_mshr_hits 64 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits_0 64 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency 3783500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency_0 3783500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate_0 0.212411 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses 623 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses_0 623 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.icache.replacements 9 # number of replacements
|
|
system.cpu.icache.replacements_0 9 # number of replacements
|
|
system.cpu.icache.replacements_1 0 # number of replacements
|
|
system.cpu.icache.sampled_refs 623 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 319.917416 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 2310 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
system.cpu.icache.writebacks_0 0 # number of writebacks
|
|
system.cpu.icache.writebacks_1 0 # number of writebacks
|
|
system.cpu.idleCycles 18494 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches 2371 # Number of branches executed
|
|
system.cpu.iew.EXEC:branches_0 1190 # Number of branches executed
|
|
system.cpu.iew.EXEC:branches_1 1181 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop 73 # number of nop insts executed
|
|
system.cpu.iew.EXEC:nop_0 36 # number of nop insts executed
|
|
system.cpu.iew.EXEC:nop_1 37 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 1.425514 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 5064 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:refs_0 2541 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:refs_1 2523 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 1883 # Number of stores executed
|
|
system.cpu.iew.EXEC:stores_0 944 # Number of stores executed
|
|
system.cpu.iew.EXEC:stores_1 939 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
|
|
system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 10238 # num instructions consuming a value
|
|
system.cpu.iew.WB:consumers_0 5115 # num instructions consuming a value
|
|
system.cpu.iew.WB:consumers_1 5123 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 15036 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:count_0 7510 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:count_1 7526 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 1.535845 # average fanout of values written-back
|
|
system.cpu.iew.WB:fanout_0 0.766960 # average fanout of values written-back
|
|
system.cpu.iew.WB:fanout_1 0.768885 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 7862 # num instructions producing a value
|
|
system.cpu.iew.WB:producers_0 3923 # num instructions producing a value
|
|
system.cpu.iew.WB:producers_1 3939 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 1.369150 # insts written-back per cycle
|
|
system.cpu.iew.WB:rate_0 0.683846 # insts written-back per cycle
|
|
system.cpu.iew.WB:rate_1 0.685303 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 15186 # cumulative count of insts sent to commit
|
|
system.cpu.iew.WB:sent_0 7583 # cumulative count of insts sent to commit
|
|
system.cpu.iew.WB:sent_1 7603 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 992 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 8 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 3912 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 367 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 2233 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 19338 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 3181 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts_0 1597 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts_1 1584 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 917 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 15655 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 1515 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 70 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 973 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 300 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.1.forwLoads 45 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.1.memOrderViolation 61 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.1.squashedLoads 981 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.1.squashedStores 309 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 131 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 807 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 185 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc_0 0.512111 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_1 0.512020 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.024130 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 8256 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 2 0.02% # Type of FU issued
|
|
IntAlu 5550 67.22% # Type of FU issued
|
|
IntMult 1 0.01% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 2 0.02% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 1728 20.93% # Type of FU issued
|
|
MemWrite 973 11.79% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:FU_type_1 8316 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1.start_dist
|
|
No_OpClass 2 0.02% # Type of FU issued
|
|
IntAlu 5613 67.50% # Type of FU issued
|
|
IntMult 1 0.01% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 2 0.02% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 1726 20.76% # Type of FU issued
|
|
MemWrite 972 11.69% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1.end_dist
|
|
system.cpu.iq.ISSUE:FU_type 16572 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type.start_dist
|
|
No_OpClass 4 0.02% # Type of FU issued
|
|
IntAlu 11163 67.36% # Type of FU issued
|
|
IntMult 2 0.01% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 4 0.02% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 3454 20.84% # Type of FU issued
|
|
MemWrite 1945 11.74% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 198 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_cnt_0 95 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_cnt_1 103 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011948 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_busy_rate_0 0.005733 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_busy_rate_1 0.006215 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 14 7.07% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 119 60.10% # attempts to use FU when none available
|
|
MemWrite 65 32.83% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 10982
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 4716 4294.30%
|
|
1 1863 1696.41%
|
|
2 1568 1427.79%
|
|
3 1132 1030.78%
|
|
4 836 761.25%
|
|
5 492 448.01%
|
|
6 274 249.50%
|
|
7 79 71.94%
|
|
8 22 20.03%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 1.509015 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 19223 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 16572 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 7181 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 4476 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency_0 4770.547945 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 2770.547945 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 696500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency_0 696500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 404500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 404500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 824 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses_0 824 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency_0 4751.219512 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2751.219512 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits_0 4 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 3896000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency_0 3896000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate_0 0.995146 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 820 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses_0 820 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 2256000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2256000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.995146 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 820 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses_0 820 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 4482.142857 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 2482.142857 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 125500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency_0 125500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 69500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 69500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.005051 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 970 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses_0 970 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency_0 4754.140787 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2754.140787 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits_0 4 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 4592500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency_0 4592500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate_0 0.995876 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 966 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses_0 966 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2660500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency_0 2660500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate_0 0.995876 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 966 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses_0 966 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 970 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses_0 970 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency_0 4754.140787 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2754.140787 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 4 # number of overall hits
|
|
system.cpu.l2cache.overall_hits_0 4 # number of overall hits
|
|
system.cpu.l2cache.overall_hits_1 0 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 4592500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency_0 4592500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate_0 0.995876 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 966 # number of overall misses
|
|
system.cpu.l2cache.overall_misses_0 966 # number of overall misses
|
|
system.cpu.l2cache.overall_misses_1 0 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2660500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency_0 2660500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate_0 0.995876 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 966 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses_0 966 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.replacements_0 0 # number of replacements
|
|
system.cpu.l2cache.replacements_1 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 792 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 429.647178 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.l2cache.writebacks_0 0 # number of writebacks
|
|
system.cpu.l2cache.writebacks_1 0 # number of writebacks
|
|
system.cpu.numCycles 10982 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 592 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IdleCycles 14764 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 762 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 26692 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 21016 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 15806 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 3542 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 1515 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 817 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 7704 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 503 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 2234 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 7 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
|
|
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|